DanieleParravicini
Graduated with honours in Computer Science and Engineering at Politecnico di Milano.
Synthara AGZurich
Pinned Repositories
ACCL
MPI-like collectives for Xilinx Alveo FPGAs
DanieleParravicini
DL-CompetitionsDatasets
Repo holding Datasets for DL-competitions A2NDL 2019-2020
elf2vmem
FastMST
Project for Advanced Algorithm and Parallel Programming course. Academic Year 2018-2019
IACV_2019
Project Image analysis and computer vision 2019-2020
re2compiler
A compiler for regex coprocessor https://github.com/DanieleParravicini/regex_coprocessor
regex_coprocessor
An accelerator to which you can offload RE matching and that does not use backtracking
vcdvcd
Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
DL-Competition
Repo for the 'Artificial Neural Networks and Deep Learning' competition - 2019/2020
DanieleParravicini's Repositories
DanieleParravicini/regex_coprocessor
An accelerator to which you can offload RE matching and that does not use backtracking
DanieleParravicini/FastMST
Project for Advanced Algorithm and Parallel Programming course. Academic Year 2018-2019
DanieleParravicini/IACV_2019
Project Image analysis and computer vision 2019-2020
DanieleParravicini/re2compiler
A compiler for regex coprocessor https://github.com/DanieleParravicini/regex_coprocessor
DanieleParravicini/ACCL
MPI-like collectives for Xilinx Alveo FPGAs
DanieleParravicini/DanieleParravicini
DanieleParravicini/DL-CompetitionsDatasets
Repo holding Datasets for DL-competitions A2NDL 2019-2020
DanieleParravicini/elf2vmem
DanieleParravicini/vcdvcd
Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
DanieleParravicini/xacc
Xilinx Adaptive Compute Research Clusters (XACC) Resources Page