DanieleParravicini

DanieleParravicini's Stars

• isocpp/CppCoreGuidelines

  The C++ Core Guidelines are a set of tried-and-true guidelines, rules, and best practices about coding in C++

  Language:CSS42.7k2k1.2k5.4k

• google-research/tuning_playbook

  A playbook for systematically maximizing the performance of deep learning models.

  27k286412.2k

• adobe-fonts/source-code-pro

  Monospaced font family for user interface and coding environments

  Language:CSS19.9k6132491.6k

• pybind/pybind11

  Seamless operability between C++11 and Python

  Language:C++15.7k2472.1k2.1k

• microsoft/language-server-protocol

  Defines a common protocol for language servers.

  Language:HTML11.2k2631.1k799

• android-password-store/Android-Password-Store

  Android application compatible with ZX2C4's Pass command line application

  Language:Kotlin2.6k76900263

• mortbopet/Ripes

  A graphical processor simulator and assembly editor for the RISC-V ISA

  Language:C++2.6k47213274

• llvm/circt

  Circuit IR Compilers and Tools

  Language:C++1.7k2562.1k296

• riscv-non-isa/riscv-asm-manual

  RISC-V Assembly Programmer's Manual

  Language:Makefile1.4k7745238

• olofk/serv

  SERV - The SErial RISC-V CPU

  Language:Verilog1.4k3858188

• lowRISC/ibex

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  Language:SystemVerilog1.4k97834541

• arduino/ArduinoCore-avr

  The Official Arduino AVR core

  Language:C1.2k673581.1k

• riscv-software-src/riscv-tools

  RISC-V Tools (ISA Simulator and Tests)

  Language:Shell1.1k121229447

• riscv-non-isa/riscv-elf-psabi-doc

  A RISC-V ELF psABI Document

  Language:Python70070173163

• olofk/edalize

  An abstraction library for interfacing EDA tools

  Language:Python63133163189

• VLSI-EDA/PoC

  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

  Language:VHDL546585594

• riscv/riscv-debug-spec

  Working Draft of the RISC-V Debug Specification Standard

  Language:Python4567342992

• geluk/pass-winmenu

  An easy-to-use password manager for Windows, compatible with pass.

  Language:C#385511425

• treee111/wahooMapsCreator

  Create maps for Wahoo device based on latest OSM maps

  Language:Python2591010326

• pulp-platform/bender

  A dependency management tool for hardware projects.

  Language:Rust245116237

• riscv/riscv-fast-interrupt

  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

  Language:Makefile2455326849

• adobe-type-tools/box-drawing

  Python script to draw all the box drawing characters and block elements based on parameters.

  Language:Python14611541

• mathis-s/SoomRV

  A simple superscalar out-of-order RISC-V microprocessor

  Language:SystemVerilog1413179

• pulp-platform/FlooNoC

  A Fast, Low-Overhead On-chip Network

  Language:SystemVerilog13272321

• mortbopet/VSRTL

  Visual Simulation of Register Transfer Logic

  Language:C++8975718

• firesim/firechip

  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

  Language:C5631031

• maltanar/gemmbitserial

  Fast matrix multiplication for few-bit integer matrices on CPUs.

  Language:Objective-C277010

• riscvarchive/riscv-eabi-spec

  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.

  2624125

• tum-ei-eda/seal5

  Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization

  Language:Python123956

• jrrk2/ibex

  Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

  Language:SystemVerilog2101