Pinned Repositories
apb_timer
cellrv32
:electron: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.
cellrv32-riscof
RISCOF platform to check the CELLRV32 for RISC-V ISA compatibility.
github-beginer
NN_RGB_FLAPPY_BIRD
:bird: A game of flappy bird for one player, play by controlling the bird using a hand tracking mechanism
SNC_core
Face-Detection-on-FPGA
This a complete and fully working Viola-Jones face detection algorithm described in VHDL and verified on the DE2-115 FPGA board.
opencv
Open Source Computer Vision Library
neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
neorv32-riscof
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
DatNguyen97-VN's Repositories
DatNguyen97-VN/cellrv32
:electron: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.
DatNguyen97-VN/apb_timer
DatNguyen97-VN/cellrv32-riscof
RISCOF platform to check the CELLRV32 for RISC-V ISA compatibility.
DatNguyen97-VN/github-beginer
DatNguyen97-VN/NN_RGB_FLAPPY_BIRD
:bird: A game of flappy bird for one player, play by controlling the bird using a hand tracking mechanism
DatNguyen97-VN/SNC_core