Divya-i
Hi there! I'm Divya, a passionate Verification Engineer with a keen interest in hardware design and verification methodologies. 🔠Verification Engineer
Pinned Repositories
100daysofRTL
Starting the "100 Days of RTL Challenge" has been an exciting adventure. Each day, I'm diving into Verilog-based RTL design, exploring the world of digital circuits. From understanding basic gates to tackling complex sequential circuits, these 100 days are helping me become a proficient RTL designer.
Divya-i
PROJECTS
System_Verilog
Divya-i's Repositories
Divya-i/100daysofRTL
Starting the "100 Days of RTL Challenge" has been an exciting adventure. Each day, I'm diving into Verilog-based RTL design, exploring the world of digital circuits. From understanding basic gates to tackling complex sequential circuits, these 100 days are helping me become a proficient RTL designer.
Divya-i/Divya-i
Divya-i/PROJECTS
Divya-i/System_Verilog