Divya-i/100daysofRTL

Starting the "100 Days of RTL Challenge" has been an exciting adventure. Each day, I'm diving into Verilog-based RTL design, exploring the world of digital circuits. From understanding basic gates to tackling complex sequential circuits, these 100 days are helping me become a proficient RTL designer.

100daysofRTL

"Hi👋, I'm Divya Sai Iruku, and I'm passionate about VLSI🎯. I've taken up the exciting 1️⃣0️⃣0️⃣ Days of RTL Challenge to enhance my skills in RTL design and verification using Verilog, SystemVerilog, and UVM. Through consistent practice and dedication, I aim to become proficient in RTL design.

During this challenge, I'll be using EDA Playground🚀 to implement RTL codes👨🏼‍💻 and work on various projects that will sharpen my understanding of digital circuits and VLSI principles.

I understand that mastery takes time and continuous learning, and the 1️⃣0️⃣0️⃣ Days of RTL Challenge provides the perfect opportunity to make significant progress in my coding abilities.

Being part of the VLSI community, I look forward to sharing my journey, learning from others, and celebrating our collective passion for RTL design! Happy learning!🎉"

📎 Here is the list of day-wise RTL Codes:

Day 1 -> Gate Level Modeling Style

Day 2 -> Data Flow Modeling Style

Day 3 -> Behavioral Modeling Style