Pinned Repositories
verilog-ethernet
Verilog Ethernet components for FPGA implementation
2022AdventOfCode
in rust
2023AdventOfCode
Advent of Code in Rust (for real this time)
FlockSentry
Open-source affordable system to automatically detect predators and save chickens.
graphing_calc
Graphing calculator implemented on an FPGA. Enter commands over UART and display results over VGA.
PositProcessingUnit
open-source HDL model, testbench, and synthesis results for a custom IEEE posit calculator
spaceapps2021
spaceapps2022
Team: Jupiter Isn't Real
vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
kria-bist
EdwinEstep's Repositories
EdwinEstep/FlockSentry
Open-source affordable system to automatically detect predators and save chickens.
EdwinEstep/2022AdventOfCode
in rust
EdwinEstep/2023AdventOfCode
Advent of Code in Rust (for real this time)
EdwinEstep/graphing_calc
Graphing calculator implemented on an FPGA. Enter commands over UART and display results over VGA.
EdwinEstep/PositProcessingUnit
open-source HDL model, testbench, and synthesis results for a custom IEEE posit calculator