/ExploreMIPS

A simple 5-stage pipelined MIPS CPU.

Primary LanguageVerilogMIT LicenseMIT

ExploreMIPS

Introduction

ExploreMIPS is a simple 5-stage pipelined MIPS CPU implemented in Verilog. The architecture of CPU solved simple hazard problems.

The below instructions are implemented.

References

[1] lvyufeng/step_into_mips

[2] Computer Organization and Design, The Hardware/Software Interface