EternitYjl

EternitYjl's Stars

• unicorn-engine/unicorn

  Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

  Language:C7.5k2141.1k1.3k

• speed47/spectre-meltdown-checker

  Reptar, Downfall, Zenbleed, ZombieLoad, RIDL, Fallout, Foreshadow, Spectre, Meltdown vulnerability/mitigation checker for Linux & BSD

  Language:Shell3.8k177285476

• eugene-tarassov/vivado-risc-v

  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

  Language:Tcl82036204187

• Eugnis/spectre-attack

  Example of using revealed "Spectre" exploit (CVE-2017-5753 and CVE-2017-5715)

  Language:C7554113170

• IAIK/transientfail

  Website and PoC collection for transient execution attacks

  Language:C165211737

• RALC88/riscv-vectorized-benchmark-suite

  RiVEC Bencmark Suite

  Language:C++885642

• riscv-boom/boom-attacks

  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)

  Language:C596316

• cispa/Security-RISC

  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)

  Language:C51615

• RALC88/gem5

  This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

  Language:C++193412

• RPTU-EIS/upec-boom-verification-suite

  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks based on the Unique Program Execution Checking (UPEC) approach.

  Language:Verilog15302

• proteus-core/prospect

  ProSpeCT: Provably Secure Speculation for the Constant-Time Policy.

  Language:C14301

• riscv-spectre-mitigations/Spectre-v2-v5-mitigation-RISCV

  Language:C91

• CTSRD-CHERI/Test-Suite-Transient-Execution

  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly

  Language:Assembly71

• sabbaghm/sonicboom-attacks

  SonicBOOM Spectre Attacks

  Language:C7200

• RPTU-EIS/SecureBOOM

  Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown and Spectre)

  Language:Verilog6001

• lapnd/BOOMv3-eager-delay

  Patched version of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. Meltdown and Spectre vulnerabilities

  Language:Scala3000

• MoeinGhaniyoun/BOOMv3-SpecShield

  SpecShield Transient Execution Attack Mitigation Techniques Implemented on BOOM

  Language:Scala3100

• RVsecurity/Spectre-Attacks-in-BOOMv3

  Language:C2

• sumukhmarathe/RISCV-Spectre-Attack-and-Defense

  EECS 573 Project

  Language:C++20