FangCunWuChang
A DAW(Digital Audio Workstation) and virtual singers developer.
Hefei University of TechnologyXuancheng, Anhui Province, China
FangCunWuChang's Stars
VikParuchuri/marker
Convert PDF to markdown quickly with high accuracy
niXman/mingw-builds-binaries
MinGW-W64 compiler binaries
LiteHttpd/LiteHttpd
A super lightweight HTTP service framework.
abhigna/fcgi-client
A simple fcgi_client
rakyll/hey
HTTP load generator, ApacheBench (ab) replacement
actions/runner-images
GitHub Actions runner images
titinko/utsu
Vocal synthesis frontend
cadencii/cadencii
sigstore/cosign
Code signing and transparency for containers and binaries
curl/curl
A command line tool and library for transferring data with URL syntax, supporting DICT, FILE, FTP, FTPS, GOPHER, GOPHERS, HTTP, HTTPS, IMAP, IMAPS, LDAP, LDAPS, MQTT, POP3, POP3S, RTMP, RTMPS, RTSP, SCP, SFTP, SMB, SMBS, SMTP, SMTPS, TELNET, TFTP, WS and WSS. libcurl offers a myriad of powerful features
Uahh/Slscq
申论生成器(
Strrationalism/YukimiScript
Scripting language for visual novel.
LiuYunPlayer/TuneLab
libsdl-org/SDL
Simple Directmedia Layer
Do-sth-sharp/Do-sth-sharp.github.io
VocalShaper official website.
opensound-org/opensound
A One-Stop Multi-Level SoundSystem Abstraction (or say sound/audio engine). Suitable for being a solid foundation for Pro-Audio Applications(e.g. a DAW) or other sound related apps.
torvalds/linux
Linux kernel source tree
xmxoxo/connect4
重力四子棋
gchq/CyberChef
The Cyber Swiss Army Knife - a web app for encryption, encoding, compression and data analysis
openscad/openscad
OpenSCAD - The Programmers Solid 3D CAD Modeller
MMPI-CHN/MMPI-CHN.github.io
MMPI-2中文测试-全免费-带结果
diffscope/dsinfer
Low level library for DiffSinger onnx model inference.
openvpi/DiffSinger
An advanced singing voice synthesis system with high fidelity, expressiveness, controllability and flexibility based on DiffSinger: Singing Voice Synthesis via Shallow Diffusion Mechanism
seerge/g-helper
Lightweight Armoury Crate alternative for Asus laptops and ROG Ally. Control tool for ROG Zephyrus G14, G15, G16, M16, Flow X13, Flow X16, TUF, Strix, Scar and other models
HFUT-CHEATER/HFUTCheaterCollection
Hefei University of Technology 投稿、举报、监督、咨询Email:hfutcheater@proton.me https://hfutcheater.gitbook.io/hfutcheater | https://hfut-cheater.github.io 合肥工业大学 安徽 作弊 造假 贪污 论文抄袭 贿赂 包庇 权力寻租 挪用基金 组织舞弊 越南留学生反华 南沙群岛 购买比赛 集体舞弊|作弊封神榜 包庇行政名单
Mostafa-Hassanien/-A-32-bit-5-stage-Pipelined-MIPS-based-RISC-Core-based-on-Harvard-Architecture-
This project aims to implement a 32-bit 5-stage pipelined High-performance MIPS-based RISC Core based on Harvard Architecture. The MIPS processor was designed using MIPS ISA (Instruction Set Architecture) and divided into three main modules: datapath unit, control unit, and hazard unit. The processor is tested to run two programs: GCD Calculation of two numbers and Factorial Calculation of a number. Programs are written in MIPS assembly code, then converted to machine code. Verilog HDL language is used on ModelSim Simulation tool to verify the functional simulation of the processor and compare between five-stage pipelined MIPS processor and single-cycle MIPS processor regarding performance analysis. Keywords: Pipelined MIPS Processor, Harvard Architecture, MIPS Assembly, Functional Simulation, Datapath, Hazard Unit.
IY2002/CPU
🖥️ 5-Stage MIPS CPU: A Verilog-based implementation of a pipelined MIPS processor, showcasing proficiency in computer architecture, RISC design principles, and hardware description languages. 🧠💡
MaxXSoft/Fuxi
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
stdware/qwindowkit
Cross-platform frameless window framework for Qt. Support Windows, macOS, Linux.
kilapas/libV5SDK