FilippoCheein

Cal Poly Electrical Engineering Alumni. Interested in FPGA, ASIC & Embedded Systems

San Luis Obispo, CA

Pinned Repositories

CNN_Reuse
Language:Python0 1 00
FPGA_Design
Language:Verilog00
Optimized_Sobel_Filter_RPI
Language:C++10
Path-Planning
Language:MATLAB3 2 00
PedalPi
Language:C1 1 00
RISCV_CPU_Pipepline
Language:SystemVerilog11
RISCV_SUPERSCALAR
Language:SystemVerilog11
Runge_Kutta_FPGA
Language:Verilog31

FilippoCheein's Repositories

FilippoCheein/Path-Planning
Language:MATLAB3 2 00
FilippoCheein/Runge_Kutta_FPGA
Language:Verilog31
FilippoCheein/Optimized_Sobel_Filter_RPI
Language:C++10
FilippoCheein/PedalPi
Language:C1 1 00
FilippoCheein/RISCV_CPU_Pipepline
Language:SystemVerilog11
FilippoCheein/RISCV_SUPERSCALAR
Language:SystemVerilog11
FilippoCheein/CNN_Reuse
Language:Python0 1 00
FilippoCheein/FPGA_Design
Language:Verilog00