GGba0

GGba0's Stars

• troyguo/awesome-dv

  Awesome ASIC design verification

  28812169

• courageheart/AMBA_APB_SRAM

  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

  Language:SystemVerilog1664064

• Siddhi-95/AHB-to-APB-Bridge-Verification

  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

  Language:SystemVerilog851120

• PacoReinaCampo/MPSoC-DV

  Multi-Processor System on Chip verified with UVM/OSVVM/FV

  Language:SystemVerilog283015

• hanysalah/uart2bustestbench

  UVM Verification IP to uart2bus IP.

  Language:SystemVerilog21208

• zli87/Wishbone-to-I2C-bus-controller-IP-Verification

  ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.

  Language:VHDL18207

• techvinodreddy/UART-IP-CORE16550A-Verification-UVM

  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a modem or other external devices, like another computer using a serial cable and RS232 protocol. This core is designed to be maximally compatible with the industry-standard National Semiconductors’ 16550A device.

  Language:Verilog17203

• muguang123/AXI_Verification

  Verification AXI-4 bus standard using UVM and System Verilog

  Language:SystemVerilog15202

• alice820621/A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM

  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence generates addresses and allows the driver to tell the BFM which slave to choose. Subsequently four monitors and scoreboards record each slave’s test results.

  Language:SystemVerilog14104

• wbbbbbb123/UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design

  Language:Verilog14202

• PacoReinaCampo/MPSoC-NTM

  Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV

  Language:SystemVerilog12202

• Harshil1995/I2C_UVM_APB

  Formulated testbench using System Verilog and UVM and verified I2C bus controller with APB interface

  Language:SystemVerilog11101

• jchengX/MAC_BFM

  wifi

  Language:SystemVerilog11102

• semify-eda/go.debug

  Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

  Language:SystemVerilog10303

• kumarrishav14/arm_watchdog

  Verification IP for Watchdog

  Language:SystemVerilog9144

• VimfulDang/APB-SPI-Controller-Verification

  UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC24xx microcontroller specification.

  Language:SystemVerilog8105

• Elias-Rosales/MIPSVerification_UVM

  Verification of a MIPS Multi-Cycle Microprocessor using UVM

  Language:SystemVerilog7102

• AkshayXPatil/Design-verification

  UVM and Systemverilog based test benches for functional verification of a RAM module

  Language:SystemVerilog6005

• chanum/uvm_spi_apb_verification

  Language:SystemVerilog5200

• dave41266/cpu8080-alu

  UVM code to verify ALU

  Language:SystemVerilog42

• funannoka/SoC-verification-using-UVM

  Language:SystemVerilog4101

• cn9826/SDR_CTRL_UVM

  EE382M-Verification course project

  Language:Verilog3

• kruegz/cpu

  CPU design with SystemVerilog/UVM verification

  Language:SystemVerilog3202

• Vivek-Dave/UVM_TestBench_For_S_R_Latch

  Simple and Complete UVM TestBench For Verification Of S R Latch

  Language:SystemVerilog3102

• dhaivat7/RISC_CPU

  RTL Design and Verification using SystemVerilog.

  Language:SystemVerilog2100

• Vivek-Dave/UVM_TeatBench_For_ROM

  Complete UVM TestBench for verification of ROM

  Language:SystemVerilog22

• charrich97/Decode_Verification

  Decoder UVM Testbench

  Language:SystemVerilog1

• mehaltalukder/ALU_UVM_Project

  Verification of a 8-bit ALU design using UVM (Universal Verification Methodology) and SystemVerilog

  Language:SystemVerilog1

• Ravikumar0110/G2UVM_sig_access_UVM_verification

  Language:SystemVerilog11

• RevanthNandamuri1341b0/ALU-Verification-Environment

  Development UVM Verification Environment for ALU DUT

  Language:SystemVerilog1103