GraphSAINT/GNN-ARCH
[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
Verilog
Stargazers
- 1Jerry2Zhao3
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- ArronLam-502
- chenshih1
- chenxuhaoMIT
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- ethanwang0921
- Fengge259
- Guohua-W
- hongsunjang@AIS_SNU, SNU ECE
- HunosiChina, Guangzhou
- Jacky-0918
- jaeyong-songGrad Student@AISys, Seoul National University
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- WuDan0399National University of Singapore
- wuying39
- wwwwyl
- xfzhou01RCSL @ HKUST
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