HHHHorrible

HHHHorrible's Stars

• excalidraw/excalidraw

  Virtual whiteboard for sketching hand-drawn like diagrams

  Language:TypeScript80.2k3963.5k7.4k

• slidevjs/slidev

  Presentation Slides for Developers

  Language:TypeScript32.5k1361k1.3k

• dennybritz/reinforcement-learning

  Implementation of Reinforcement Learning Algorithms. Python, OpenAI Gym, Tensorflow. Exercises and Solutions to accompany Sutton's Book and David Silver's course.

  Language:Jupyter Notebook20.4k8601556k

• thunlp/WantWords

  An open-source online reverse dictionary.

  Language:JavaScript7k7149618

• peng-zhihui/XUAN

  5.4k10234823

• learnables/learn2learn

  A PyTorch Library for Meta-learning Research

  Language:Python2.6k32259349

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.6k581362

• sudharsan13296/Awesome-Meta-Learning

  A curated list of Meta Learning papers, code, books, blogs, videos, datasets and other resources.

  1.5k692300

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.4k5270433

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1k39118252

• tristandeleu/pytorch-maml-rl

  Reinforcement Learning with Model-Agnostic Meta-Learning in Pytorch

  Language:Python8151560157

• XMuli/ChineseChess

  Cross-platform and online battle platform game based on Qt: Chinese Chess. Also known as:『Xiangqi』『**象棋』

  Language:C++6851219183

• veeresht/CommPy

  Digital Communication with Python

  Language:Python5453566177

• ZipCPU/wb2axip

  Bus bridges and other odds and ends

  Language:Verilog467315296

• taichi-ishitani/tvip-axi

  AMBA AXI VIP

  Language:SystemVerilog3481637102

• cnych/markdown-weixin

  一个在线将 Markdown 转换为微信公众帐号文章格式的工具

  Language:JavaScript27221663

• loykylewong/FPGA-Application-Development-and-Simulation

  《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

  Language:SystemVerilog1234127

• waviousllc/wav-lpddr-hw

  Wavious DDR (WDDR) Physical interface (PHY) Hardware

  Language:SystemVerilog9419437

• froger-me/wp-weixin

  WordPress WeChat integration

  Language:PHP87103338

• CoreyChen922/sata3_host_controller

  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.

  Language:Verilog607048

• muneebullashariff/axi4_vip

  Verification IP for APB protocol

  Language:SystemVerilog5537

• bmartini/verilog-arbiter

  A look ahead, round-robing parametrized arbiter written in Verilog.

  Language:Verilog402222

• CospanDesign/nysa-verilog

  Verilog Repository for GIT

  Language:Verilog286121

• alexforencich/verilog-mersenne

  Verilog implementation of Mersenne Twister PRNG

  Language:Python245011

• wenxuan-hu/SSRL_work

  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework

  Language:SystemVerilog215

• PaserTech-Hardware/GowinDDR3_AXI4_SpinalHDL

  Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现

  Language:Verilog18236

• diadatp/nasti-ddrx-mc

  NASTI slave compliant DDRx memory controller.

  Language:SystemVerilog11611

• kevinbdsouza/mmWave

  Comparative analysis of mmWave channel models

  Language:Matlab114010

• vlsi1217/BPSK_ASIC

  BPSK demodulator ASIC design with Toshiba 45nm lib in verilog for EE 287 Spring 2013

  Language:Verilog10202

• anishmadan23/MAML_Pytorch_RL

  Language:Python9200