Issues
- 0
axil_fifo
#82 opened by 0TulipRose0 - 1
`axi_dma_wr` does not respect TKEEP
#81 opened by KireinaHoro - 6
- 0
Parameters not passed on to axi_crossbar_wr and axi_crossbar_rd in axi_crossbar.v
#79 opened by RiceShelley - 2
about AXI DMA
#76 opened by zengzhengqi0524 - 3
Q: DMA, desc_len VS tlast in axi_dma_wr
#78 opened by abarajithan11 - 14
Performing multiple beat transfer
#77 opened by ManjunathKalmath - 2
cocotb makefile
#75 opened by ManjunathKalmath - 2
About AXI_FULL_CDC
#74 opened by LZR1567 - 2
about axi_ram
#73 opened by nViol3t - 3
AXI_Register hangs when SIM=verilator
#72 opened by ManjunathKalmath - 3
about AXI_VFIFO
#59 opened by Monster-Kee - 4
- 14
About the solution for deadlocks
#70 opened by omeag - 1
about tb
#69 opened by Unicorn619 - 2
About width missmatch
#68 opened by a60626316 - 6
Axi DMA consistently returns DECERR
#66 opened by EnricoGiordano1992 - 0
Timing issues with `axi_dma_wr`
#67 opened by KireinaHoro - 6
- 4
Q: is there any component for read data out of standard ram/fifo and then transfer the data to axi master
#64 opened by constant007 - 0
about axi_ram design specification
#63 opened by Maani02 - 2
- 14
AxiLiteMaster hangs with Verilator
#48 opened by catkira - 2
- 2
AXI Lite interconnect in N to 1 configuration
#54 opened by Twistix - 0
- 1
axi_interconnect Synthesis
#55 opened by GGbang2 - 10
Why assume packet smaller than max burst size when AXI_MAX_BURST_SIZE >=4096?
#56 opened by qiweiii-git - 0
AXI Reset Signal
#53 opened by mkokki - 4
About priority_encoder
#52 opened by GGbang2 - 6
- 2
AXI interconnect
#51 opened by ilamparithy01 - 3
Documentation for axil_interconnect
#50 opened by catkira - 2
tb simulation failed
#45 opened by nashsrg - 8
- 12
- 2
- 0
axil_ram. How to adjust rvaild delay.
#36 opened by cjhonlyone - 2
question: how to read this syntax?
#35 opened by hughperkins - 0
Circular logic in axi_crossbar
#34 opened by MikeWalrus - 1
AXI DMA never gives out a ready HIGH
#33 opened by jasonzzzzzzz - 2
- 4
- 6
About axil-interconnect
#26 opened by omeag - 0
Support read data interleaving
#30 opened by alexforencich - 6
- 4
- 2
CDC module
#25 opened by omeag - 1
About VCS Compile
#24 opened by dybzcx - 3
About CDC module
#23 opened by omeag