5 days workshop on RTL design with Sky130 PDK.
- Day 1: Introduction to Verilog RTL design and Synthesis
To prepare the environment, OPENLANE and install the Sky130 PDK.
First of all, create a folder named VLSI and clone all the files from https://github.com/kunalg123?tab=repositories
You need to clone 4 repositories: sky130RTLDesignAndSynthesisWorkshop, sky130CircuitDesignWorkshop, vsdflow and SystemDesignWorkshopCollaterals
You can use cd to enter the VLSI folder and 'ls' to show the existing files:
Once you prepared the environemnt, you can use 'ls' to check all the flies in each folder. The folder 'sky130RTLDesignAndSynthesisWorkshop' contains all the verilog files needed for this workshop: verilog files and test bench files for all the labs.
At this level the setup is done! You can simulate and synthesis your models. The 'verilog_files' folder contains the verilog file and the associated corresponding test bench file of each project. The test bench file is named with 'tb_FileName.v' Use 'iverilog' to lood the files: good_mux.v and tb_good_mux.v Then wwe're going to execute the '.a/a.out' file to dump the dcv file. (out put of the simulator will be cvd file) After that, you can run the simulator, gtkwave by runing the command: getkwavr tb_good_mux.vcd You should use the VCD file generated previously, not use the 'tb_File" The simulator will show all the signals, zoom and select a region for better understanding.
The next figure shows the difference between the two files: good_mux.v and tb_good_mux.v
Synthesizer: yosys yosys is a synthesyser translating the design using a library into a netlist file. To call yosys, use the command 'yosys' We will use three commands:
- read_verilog:to read the design
- Read library: read the .lib file
- write_verilog: write out the netlist file as an outpu which is a representation of the design in form of standard cells
During the synthesis the RTL is converted into gates and the connections are made between the gates, generating a netlist file.
Synthesis a design: Invoque yosys with the command: 'yosys' Once you're in the yosys promp, you should read the library with : 'read_liberty -lib ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib'
You should read the verilog files with 'read_verilog' The next step is to synthesis the verilog file using the command line: 'synth -top good_mux' Do not put the extension'.v' because it's the name of the top module name.
Now, you can generate the netlist using the command 'abc -liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib' abc is the command to convert the rtl file into gate level and we need to specify the library file to be used. It shows all the cells and the resurces used. We can use the command 'show' to show the graphical logic that has beed realized.
- Day 2: Timing library hierarchical vs flat synthesis and efficient flop coding styles
In this session, you're going to work on the module: multiple_modules.v and tb_multiple_modules.v
Launch yosys then read the liberty file with :'yosys' then 'read_liberty -lib ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib' then 'read_verilog multiple_modules.v' 'synth -top multiple_modules' the reoport shows all the resource used in details. Now usse 'abc -liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib'
If you use 'show' to see the module, yosys will show an error because it's a multiple modules. To see the netlist, you should use 'show multiple_modules", you need to specify the name of the module.
'flatten' is a command used to write a flat netlist. execute 'flatten' on the this module. then use 'write_verilog multiple_modules_flat.v' to write the flatten file and open it with (!gvim) or gedit and compare with the original file.
Now, let's sythesis the multiple modules and see how it works. Close yosys and open it again to. then execute the commands to read, and produce the netlist and synthesys. (same as prevousily) after the 'abc' command. Use the 'flatten' to to extend the modules then use 'show' to present the modules.
For a multiple modules, we can do the synthesis of each module alone. Let load the design agian and synthesize the sub_module1. Use the command: 'synth -top sub_module1' We will see the report showing only one used cell in the instance sub_module1. Use the abc then show to see the sub module1. If we have a design using a same intance in multiple places, we can synthesize one sub module once, then replicate it as many times you need. It saves time anad money!
We alos use this to divide the complex design for better understanding and control it.
Various Flop Coding Styles and optimization
Various Flop Coding Styles and optimization
idir@ubuntu-m-2vcpu-16gb-sgp1-01:~/VLSI/sky130RTLDesignAndSynthesisWorkshop/verilog_files$ iverilog dff_asyncres.v tb_dff_asyncres.v
idir@ubuntu-m-2vcpu-16gb-sgp1-01:~/VLSI/sky130RTLDesignAndSynthesisWorkshop/verilog_files$ ./a.out
VCD info: dumpfile tb_dff_asyncres.vcd opened for output.
idir@ubuntu-m-2vcpu-16gb-sgp1-01:~/VLSI/sky130RTLDesignAndSynthesisWorkshop/verilog_files$ gtkwave tb_dff_asyncres.vcd
GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[0] start time.
[3000000] end time.
Open the file dff_asyncres.v and its assigned testbench tb_asyncres.v and proceed to the regulal flow for synthesis
The gtkwave simulator will show the simulation results:
- Day 3: Combinational and Sequential optimization
In this section we will use the optimization files located in verilog_files.
Use the command 'ls opt' to show all the existing files:
the opt_check.v is as follows: module opt_check (input a , input b , output y); assign y = a?b:0; endmodule
Let's start with the process: load yosys and the library Liberty. After synthesis, we execute the following command :
yosys> opt_clean -purge
5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \opt_check..
then link it to 'liberty' and use show:
In opt_check2.v, the impact of simplifiv=cation will shown on RTL
After adapting to liberty library with 'abc'command, 'opt_clean -purge' should be executed
The results are shown next:
- Day 4: GLS, blocking vs non-blocking and Synthesis-Simulation mismatch
To run GLS, we need a netlist, the verilog models and the testbench. We submitt all these files to iverilog.
Now, synthesis the model and use the 'synth -top ternary_operator_mux_net.v'
yosys> write_verilog -noattr ternary_operator_mux_net.v
5. Executing Verilog backend.
Dumping module `\ternary_operator_mux'.
yosys> show
Let's do the GLS: To do the GLS, we need to invoke iverilog with verilog file models
yosys> read_liberty -lib ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
1. Executing Liberty frontend.
Imported 428 cell types from liberty file.
yosys> abc -liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
2. Executing ABC pass (technology mapping using ABC).
yosys> exit
End of script. Logfile hash: ebd6306767
CPU: user 0.19s system 0.01s, MEM: 64.41 MB total, 35.12 MB resident
Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os)
Time spent: 91% 2x read_liberty (0 sec), 8% 1x abc (0 sec)
idir@ubuntu-m-2vcpu-16gb-sgp1-01:~/VLSI/sky130RTLDesignAndSynthesisWorkshop/verilog_files$ iverilog ../my_lib/verilog_model/primitives.v ../my_lib/verilog_model/sky130_fd_sc_hd.v ternary_operator_mux_net.v tb_ternary_operator_mux.v
idir@ubuntu-m-2vcpu-16gb-sgp1-01:~/VLSI/sky130RTLDesignAndSynthesisWorkshop/verilog_files$ ./a.out
VCD info: dumpfile tb_ternary_operator_mux.vcd opened for output.
idir@ubuntu-m-2vcpu-16gb-sgp1-01:~/VLSI/sky130RTLDesignAndSynthesisWorkshop/verilog_files$ gtkwave tb_ternary_operator_mux.vcd
GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[0] start time.
[300000] end time.
- Day 5: Day 5 - If, case, for loop and for generate