Pinned Repositories
FPGA-Design-Flow-using-Vivado
This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
kalman_mppt
mppt algorithm using kalman filter in VHDL
MachineLearningWithPython
Get started with Machine Learning with Python - An introduction with Python programming examples
Phase-Locked-Loop-Design-using-SKY130nm-Technology
Workshop, 31 July 2021 and 1 August 2021
RISC-V_MYTH_Workshop
Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for Me in Thirty Hours" Workshop
RTL-workshop-Sky130-PDK
RTL Design using Verilog with Sky130 PDK
RTL_synthesis_using_sky130
RTL_Workshop_Sky130
5 days workshop with RTL Design using Sky130 PDK. Practical training of verilog RTL design using yosys for different cases.
Vitis-Tutorials
Imellal's Repositories
Imellal/RTL-workshop-Sky130-PDK
RTL Design using Verilog with Sky130 PDK
Imellal/FPGA-Design-Flow-using-Vivado
This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
Imellal/kalman_mppt
mppt algorithm using kalman filter in VHDL
Imellal/MachineLearningWithPython
Get started with Machine Learning with Python - An introduction with Python programming examples
Imellal/Phase-Locked-Loop-Design-using-SKY130nm-Technology
Workshop, 31 July 2021 and 1 August 2021
Imellal/RISC-V_MYTH_Workshop
Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for Me in Thirty Hours" Workshop
Imellal/RTL_synthesis_using_sky130
Imellal/RTL_Workshop_Sky130
5 days workshop with RTL Design using Sky130 PDK. Practical training of verilog RTL design using yosys for different cases.
Imellal/Vitis-Tutorials