ImeshBalasuriya
Computer Engineering Undergraduate at Faculty of Engineering, University of Peradeniya.
Sri Lanka
Pinned Repositories
e17-3yp-E-Parking-System
An autonomous system for assigning and managing parking spots and payments in a car park. https://cepdnaclk.github.io/e17-3yp-E-Parking-System/
e17-4yp-Neuromorphic-NoC-Architecture-for-SNNs
This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, and test it on FPGA.
e17-6sp-Skim-Sequencing-Analysis
An Analytical Software for Next Generation Skim Sequencing Data.
e17-co326-Smart-Building
chisel-bootcamp
Generator Bootcamp Material: Learn Chisel the Right Way
CO224-Single-Cycle-CPU
CO226_Project2020
CO521-COOL-Compiler
Compiler implementation for the COOL programming language from scratch developed for the CO521 - Compilers course.
CO543-SL-Number-Plate-Detection
e17-3yp-E-Parking-System
An autonomous system for assigning and managing parking spots and payments in a car park. https://cepdnaclk.github.io/e17-3yp-E-Parking-System/
ImeshBalasuriya's Repositories
ImeshBalasuriya/chisel-bootcamp
Generator Bootcamp Material: Learn Chisel the Right Way
ImeshBalasuriya/CO224-Single-Cycle-CPU
ImeshBalasuriya/CO226_Project2020
ImeshBalasuriya/CO521-COOL-Compiler
Compiler implementation for the COOL programming language from scratch developed for the CO521 - Compilers course.
ImeshBalasuriya/CO543-SL-Number-Plate-Detection
ImeshBalasuriya/e17-3yp-E-Parking-System
An autonomous system for assigning and managing parking spots and payments in a car park. https://cepdnaclk.github.io/e17-3yp-E-Parking-System/
ImeshBalasuriya/e17-4yp-Neuromorphic-NoC-Architecture-for-SNNs
This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, and test it on FPGA.
ImeshBalasuriya/e17-co326-Smart-Building
ImeshBalasuriya/e17-co328-Skim-Sequencing-Analysis
An Analytical Software for Next Generation Skim Sequencing Data.
ImeshBalasuriya/e17-co502-RV32IM-Pipeline-Implementation-Group1
An in-order 5-stage pipelined RISC-V CPU implementation consisting of the RV32I base ISA and the M-extension for multiplication/division operations.
ImeshBalasuriya/e17-co542-network-malware-analysis
ImeshBalasuriya/ImeshBalasuriya
Config files for my GitHub profile.
ImeshBalasuriya/ImeshBalasuriya.github.io
ImeshBalasuriya/LF-Building-a-RISC-V-CPU-Core
ImeshBalasuriya/module-ballerina-log
Ballerina log Module
ImeshBalasuriya/module-ballerina-oauth2
Ballerina OAuth2 Module
ImeshBalasuriya/module-ballerina-random
Ballerina Random Library
ImeshBalasuriya/module-ballerina-uuid
Ballerina UUID Module
ImeshBalasuriya/module-ballerinax-azure-cosmosdb
ImeshBalasuriya/module-ballerinax-github
ImeshBalasuriya/module-ballerinax-mongodb
ImeshBalasuriya/people.ce.pdn.ac.lk
Student and staff profile pages website of the Department of Computer Engineering, University of Peradeniya https://people.ce.pdn.ac.lk/
ImeshBalasuriya/RV32IM-pipeline-implementation
ImeshBalasuriya/slate
Slate is a Jekyll theme for GitHub Pages
ImeshBalasuriya/Video-to-ASCII