cepdnaclk/e17-4yp-Neuromorphic-NoC-Architecture-for-SNNs
This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, and test it on FPGA.
Verilog
Issues
- 0
Implement interrupts
#6 opened by ImeshBalasuriya - 0
Implement Hazard Detection Unit
#14 opened by ImeshBalasuriya - 0
Implement FIFO unit
#10 opened by ImeshBalasuriya - 0
Implement network interface
#9 opened by ImeshBalasuriya - 1
Implement random number generator
#8 opened by ImeshBalasuriya - 0
- 0
Update project README
#2 opened by ImeshBalasuriya - 0
Add abstract section to project page
#3 opened by ImeshBalasuriya