Table of Content:
| Section No. | Action Item |
|---|---|
| 1 | Install Virtual Box,Ubuntu 20.04 |
| 2 | Install Xschem,Magic,open_pdks,netgen |
| 3 | Prelayout Simulation of Inverter using Xschem,Ngspice |
| 4 | Postlayout Simulation of Inverter using Magic,Ngspice |
| 5 | Comparing Postlayout vs Prelayout of Inverter |
| 6 | Design of Pre,Postlayout Simulations of Complex Function using General PDKs |
| 7 | LVS of Inverter,Fn Function |
- A Warmup and Getting Started with the flow with installation of Tools and Usage
| First Header | Second Header |
|---|---|
| Align | Netlist to GDS |
| Magic | Layout Editor |
| ngspice | SPICE Simulator |
| netgen | LVS,Netlist Generator |
| open_pdks | Sky130 library |
| xschem | Schematic Editor |
- ALIGN (Analog Layout, Intelligently Generated from Netlists) is to automatically translate an unannotated (or partially annotated) SPICE netlist of an analog circuit to a GDSII layout.
Follow the command to install:
for more info refer:https://github.com/sanampudig/OpenFASoC/tree/main/AUXCELL
$ export CC=/usr/bin/gcc $ export CXX=/usr/bin/g++ $ git clone https://github.com/ALIGN-analoglayout/ALIGN-public $ cd ALIGN-public $ #Create a Python virtualenv $ python -m venv general $ source general/bin/activate $ python -m pip install pip --upgrade # Install ALIGN as a USER $ pip install -v . # Install ALIGN as a DEVELOPER $ pip install -e . $ pip install setuptools wheel pybind11 scikit-build cmake ninja $ pip install -v -e .[test] --no-build-isolation $ pip install -v --no-build-isolation -e . --no-deps --install-option='-DBUILD_TESTING=ON'
-
Magic is a Open-Source Layout tool
``` $ git clone git://opencircuitdesign.com/magic $ cd magic $ ./configure $ make $ sudo make install ``` -
For more info refer: http://opencircuitdesign.com/magic/index.html
-
Ngspice is a Opensource Simulator for Electrical and Electronic Circuits
Steps to install:
After downloading the tar file from https://sourceforge.net/projects/ngspice/files/ to a local directory, it decompress and install using following:$ tar -zxvf ngspice-38.tar.gz $ cd ngspice-38 $ mkdir release $ $ cd release $ ../configure --with-x --with-readline=yes --disable-debug $ make $ sudo make install- Incase of More info refer: https://ngspice.sourceforge.io/index.html
Please note that to view the simulation graphs of ngspice, xterm is required and can be installed using.
$ sudo apt-get update # Install Xaw library $ sudo apt-get install libxaw7-dev # Install xterm $ sudo apt-get install xterm # Install bison $ sudo apt-get install bison # Install flex $ sudo apt-get install flex # Install readlines library $ sudo apt-get install libreadlines6-dev - Incase of More info refer: https://ngspice.sourceforge.io/index.html
-
Netgen is a Open Source Tool with Compares Netlists,a Process is Called as LVS,Which stands for Layout vs Schematic.
Install steps:$ git clone git://opencircuitdesign.com/netgen $ cd netgen $ ./configure $ make $ sudo make install -
Incase of any errors refer:http://opencircuitdesign.com/netgen/index.html
- Open_PDKs is distributed with files that support the Google/SkyWater sky130 open process description [https://github.com/google/skywater-pdk] (https://github.com/google/skywater-pdk)
. Open_PDKs will set up an environment for using the SkyWater sky130 process with open-source EDA tools and tool flows such as magic, qflow, openlane, netgen, klayout, etc.
$ git clone git://opencircuitdesign.com/open_pdks
$ open_pdks
$ ./configure --enable-sky130-pdk
$ make
$ sudo make install
- First lets create a working Directory for this.
$ mkdir week0 $ mkdir designs $ cd designs $ mkdir mag $ mkdir netgen $ mkdir xschem $ cd xschem $ cp /usr/local/share/pdk/sky130A/libs.tech/xschem/xschemrc $ cp /usr/local/share/pdk/sky130A/libs.tech/ngspice/spinit .spiceinit $ cd ../mag $ cp /usr/local/share/pdk/sky130A/libs.tech/magic/sky130A.magicrc .magicrc $ cd ../netgen $ cp /usr/local/share/pdk/sky130A/libs.tech/netgen//sky130A_setup.tcl - magic Check
- netgen
- xschem check
- ngspice
-
To combined Sky130 library file with xschem run the following commands.
xschem --rcfile /usr/local/share/pdk/sky130A/libs.tech/xschem/xschemrc
A Inverter Schematic is made by placing compoents from the open_pdk library.
From the VTC Graph of Inverter the Following Parameters are Measured:
Vtrip Voltage(Vtp)= 0.845
VOL= 0.09 VIH= 0.92
VOH= 1.74 VIL= 0.71
- Noise Margin :
NMl=Vil-Vol=0.71-0.09=0.62
NMh=Voh-vih=1.74-0.92=0.82
- Manual Layout of Inverter.
- After having a DRC free layout.Goto Tkcon.tcl command window to extract spice
extract do local- to save .ext and extractions to the local directory.extract do local extract all
extract all- to extract all files from magic
Extracted Netlist after Modificationsext2spice lvs ext2spice cthresh 0 rthresh 0 ext2spice
.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt X0 Vout Vin Vdd Vdd sky130_fd_pr__pfet_01v8 ad=9e+11p pd=4.9e+06u as=9e+11p ps=4.9e+06u w=2e+06u l=150000u X1 Vout Vin gnd gnd sky130_fd_pr__nfet_01v8 ad=4.5e+11p pd=2.9e+06u as=4.5e+11p ps=2.9e+06u w=1e+06u l=150000u Vin Vin GND pulse(0 1.8 1n 1n 1n 4n 8n) V2 Vdd GND 1.8 .tran 0.01n 60n .control run .endc .end
- To Run The post-layout Simulation of Inverter use the command.
ngspice <file_name>.spice
- Noise Margin Analysis of Prelayout vs Postlayout
| Pre-layout | Postlayout |
|---|---|
 |
 |
| VOL = 0.71 VOH= 1.74 VIL = 0.71 VIH = 0.92 |
VOL= 0.76 VOH= 1.73 VIL= 0.76 VIH= 0.97 |
-
For our Convencience of Test-bench the Pulse timing parameters are choosen as Manually:
Rise time : 1 ns
Fall time : 1 ns
On-Time : 4 ns
Time Period: 8 nsTransient Analysis Pre-layout Post-layout Propagation Delay(Tpd) 
Rising Propagation Delay(Tpdr) 
Falling Propagation Delay(Tpdf) 
- For more Accurate measurement use the Following measures in inverter_trans.spice
Vin Vin GND (0 1.8 50ps 10ps 10ps 200 ps 500ps) .trans 1ps 600ps - Here is the Spice Netlist:
- Output Waveform and Analysis:
- The Function Circuits layout is Designed using Euler Path
- Now Extract the Spice Netlist and Edit the Sources,Analysis in Netlist
* SPICE3 file created from fn_layout.ext - technology: min2
.option scale=0.09u
M1000 a_46_38# d a_22_38# vdd pmos w=17 l=2
+ ad=102 pd=46 as=204 ps=92
M1001 out c a_14_9# gnd nmos w=17 l=2
+ ad=204 pd=92 as=204 ps=92
M1002 vdd b a_46_38# vdd pmos w=17 l=2
+ ad=204 pd=92 as=0 ps=0
M1003 gnd f a_30_9# gnd nmos w=17 l=2
+ ad=204 pd=92 as=102 ps=46
M1004 gnd b a_14_9# gnd nmos w=17 l=2
+ ad=0 pd=0 as=0 ps=0
M1005 out e a_22_38# vdd pmos w=17 l=2
+ ad=102 pd=46 as=0 ps=0
M1006 a_14_38# a vdd vdd pmos w=17 l=2
+ ad=102 pd=46 as=0 ps=0
M1007 a_14_9# a out gnd nmos w=17 l=2
+ ad=0 pd=0 as=0 ps=0
M1008 a_30_9# e out gnd nmos w=17 l=2
+ ad=0 pd=0 as=0 ps=0
M1009 a_22_38# f out vdd pmos w=17 l=2
+ ad=0 pd=0 as=0 ps=0
M1010 a_22_38# c a_14_38# vdd pmos w=17 l=2
+ ad=0 pd=0 as=0 ps=0
M1011 a_14_9# d gnd gnd nmos w=17 l=2
+ ad=0 pd=0 as=0 ps=0
C0 a_30_9# gnd 3.37fF
C1 a_14_9# gnd 6.82fF
C2 out gnd 8.40fF
C3 a_22_38# gnd 3.02fF
C4 vdd gnd 9.58fF
* Analysis
Vdd vdd 0 1.8
V1 a 0 0 pulse 0 1.8 0.1n 10p 10p 1n 2n
V2 b 0 0 pulse 0 1.8 0.2n 10p 10p 1n 2n
V3 c 0 0 pulse 0 1.8 0.3n 10p 10p 1n 2n
V4 d 0 0 pulse 0 1.8 0.4n 10p 10p 1n 2n
V5 e 0 0 pulse 0 1.8 0.5n 10p 10p 1n 2n
V6 f 0 0 pulse 0 1.8 0.6n 10p 10p 1n 2n
***Simulation commands***
.op
.tran 10p 4n
.MEAS TRAN rise_time TRIG V(out) VAL=0.18 RISE=1 TARG V(out) VAL=1.62 RISE=1
.MEAS TRAN FALL_time TRIG V(out) VAL=1.62 FALL=1 TARG V(out) VAL=0.18 FALL=1
.save all
*** .include model file ***
.include model.mod
.end
Run Spice Simulations of Postlayout Netlist
| SI.No | Action Item |
|---|---|
| 1 | Install Align |
| 2 | Postlayout Characteristics of Inverter using Align |
| 3 | Compare Postlayout Char of Align vs Magic |
| 4 | Design and Simulation of Complex Fn using Sky130 PDKs |
| 5 | Postlayout Characteristics of Complex Function using Magic |
| 6 | Postlayout Characteristics Fn function using Align |
| 7 | LVS of Inverter And Fn function |
- ALIGN (Analog Layout, Intelligently Generated from Netlists) is to automatically translate an unannotated (or partially annotated) SPICE netlist of an analog circuit to a GDSII layout. Follow the command to install:
$ export CC=/usr/bin/gcc
$ export CXX=/usr/bin/g++
$ git clone https://github.com/ALIGN-analoglayout/ALIGN-public
$ cd ALIGN-public
$ #Create a Python virtualenv
$ python -m venv general
$ source general/bin/activate
$ python -m pip install pip --upgrade
# Install ALIGN as a USER
$ pip install -v .
# Install ALIGN as a DEVELOPER
$ pip install -e .
$ pip install setuptools wheel pybind11 scikit-build cmake ninja
$ pip install -v -e .[test] --no-build-isolation
$ pip install -v --no-build-isolation -e . --no-deps --install-option='-DBUILD_TESTING=ON'
for more info refer : https://github.com/sanampudig/OpenFASoC/tree/main/AUXCELL
- Clone the repo
git clone https://github.com/ALIGN-analoglayout/ALIGN-pdk-sky130
mvSKY130_PDKto../ALIGN-public/pdks
- Everytime we start running tool in new terminal run following commands.
python3 -m venv general source general/bin/activate - Commands to run ALIGN (goto ALIGN-public directory)
mkdir work cd work - Syntax to Generate .lef,.gds files
schematic2layout.py <NETLIST_DIR> -p <PDK_DIR> -c - Running a EXAMPLE:
schematic2layout.py ../ALIGN-pdk-sky130/examples/five_transistor_ota -p ../pdks/SKY130_PDK/ - Now open the .lef , .gds files in klayout
GDS File LEF File
|
- Create a Netlist with .sp extension.This Netlist is Different in terms of Parameters to That one Generated by Xschem.
.subckt inverter A B vdd vss
XM1 B A vdd vdd sky130_fd_pr__pfet_01v8 w=21e-7 l=0.15n nf=10 m=1
XM2 B A vss vss sky130_fd_pr__nfet_01v8 w=21e-7 l=0.15n nf=10 m=1
.ends
- Now Run the Following Move to General Environment:
schematic2layout.py ../ALIGN-pdk-sky130/examples/inverter/ -p ../pdks/SKY130_PDK/
|
-
To read the GDS file in magic Click on READ GDS and Select the INVERTER_0.gds
-
-
Here is the Modified Netlist of the Inverter after Extraction
* SPICE3 file created from INVERTER_0.ext - technology: sky130A
.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
x1 A B VDD VSS inverter
.subckt inverter A B VDD VSS
X0 B A VDD VDD sky130_fd_pr__pfet_01v8 ad=2.94e+12p pd=2.38e+07u as=3.465e+12p ps=2.85e+07u w=2.1e+06u l=150000u
X1 VDD A B VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X2 VDD A B VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X3 B A VDD VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X4 B A VDD VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X5 VDD A B VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X6 VDD A B VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X7 B A VDD VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X8 B A VDD VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X9 VDD A B VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X10 B A VSS VSS sky130_fd_pr__nfet_01v8 ad=2.94e+12p pd=2.38e+07u as=3.465e+12p ps=2.85e+07u w=2.1e+06u l=150000u
X11 VSS A B VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X12 B A VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X13 VSS A B VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X14 VSS A B VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X15 B A VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X16 B A VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X17 VSS A B VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X18 VSS A B VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
X19 B A VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=2.1e+06u l=150000u
C0 A VDD 2.60fF
C1 B VDD 4.03fF
C2 B A 1.20fF
C3 B VSS 3.35fF
C4 A VSS 2.98fF
C5 VDD VSS 5.63fF
.ends
Vgnd VSS 0 0
VDD VDD VSS 1.8
Vin A VSS 0
* create pulse
* Vin A VSS pulse(0 1.8 1p 10p 10p 1n 2n)
* create PWL
* Vin A VSS pwl(0 1.8v 5n 1.8v 5.1n 0 10n 0)
* .tran 10p 10n
.dc Vin 0 1.8 0.01
.control
run
plot A B
.endc
.end
- DC Analysis of Inverter :
- Transient Analysis :
| Parameters | Align | Manual |
|---|---|---|
| Rise Time(Tpdr) | ||
| Fall Time(Tpdf) | ||
| High to Low Propagation Delay(Tph-l) | ||
| Low to High Propagation Delay(Tpl-h) |
- Fn= [(B+D).(A+C)+E.F]'
- Schematic:
- The Netlist for Generating Fn Function:
.subckt Fn A B C D E F Y vdd vss
XM1 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=0.15e-9 W=21e-7 nf=10 m=1
XM2 net3 B vdd vdd sky130_fd_pr__pfet_01v8 L=0.15e-9 W=21e-7 nf=10 m=1
XM3 net2 C net1 net1 sky130_fd_pr__pfet_01v8 L=0.15e-9 W=21e-7 nf=10 m=1
XM4 net2 D net3 net3 sky130_fd_pr__pfet_01v8 L=0.15e-9 W=21e-7 nf=10 m=1
XM5 Y E net2 net2 sky130_fd_pr__pfet_01v8 L=0.15e-9 W=21e-7 nf=10 m=1
XM6 Y F net2 net2 sky130_fd_pr__pfet_01v8 L=0.15e-9 W=21e-7 nf=10 m=1
XM7 Y A net4 net4 sky130_fd_pr__nfet_01v8 L=0.15e-9 W=21e-7 nf=10 m=1
XM8 Y C net4 net4 sky130_fd_pr__nfet_01v8 L=0.15e-9 W=21e-7 nf=10 m=1
XM9 Y E net5 net5 sky130_fd_pr__nfet_01v8 L=0.15e-9 W=21e-7 nf=10 m=1
XM10 net4 B vss vss sky130_fd_pr__nfet_01v8 L=0.15e-9 W=21e-7 nf=10 m=1
XM11 net4 D vss vss sky130_fd_pr__nfet_01v8 L=0.15e-9 W=21e-7 nf=10 m=1
XM12 net5 F vss vss sky130_fd_pr__nfet_01v8 L=0.15e-9 W=21e-7 nf=10 m=1
.ends
Run the Get Netlist:
schematic2layout.py ../ALIGN-pdk-sky130/examples/Fn/ -p ../pdks/SKY130_PDK/
-
Here are the GDS and Lef Files in Klayout:
-
Open the GDS file in Magic
-
-
The Extracted Netlist is As Follows FN_0.spice
vinayreddy@vsd-mspdr:~/Desktop/mspdr/ALIGN-public/work/mag$ ngspice FN_0.spice
******
** ngspice-39 : Circuit level simulation program
** The U. C. Berkeley CAD Group
** Copyright 1985-1994, Regents of the University of California.
** Copyright 2001-2022, The ngspice team.
** Please get your ngspice manual from http://ngspice.sourceforge.net/docs.html
** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html
** Creation Date: Tue Feb 10 08:15:11 UTC 2023
******
Note: No compatibility mode selected!
Circuit: * spice3 file created from fn_0.ext - technology: sky130a
ngspice 2 -> plot Y
Error: no such vector Y
ngspice 3 ->
| SI.No | Action Item | Status |
|---|---|---|
| 1 | Installion of OpenFASOC and Other Dependencies | ✔️ |
| 2 | Configuring the Sky130A path | ✔️ |
| 3 | Generating Temperature Sensor Layout | ✔️ |
- OpenFASoC is a project focused on automated analog generation from user specification to GDSII with fully open-sourced tools. It is led by a team of researchers at the University of Michigan and is inspired from FASoC which sits on proprietary software.
The tool is comprised of analog and mixed-signal circuit generators, which automatically create a physical design based on user specifications.
- Run the Following Commands.
$ git clone https://github.com/idea-fasoc/openfasoc
$ sudo ./dependencies.sh
- This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.Which converts a RTL design to Gate-level Netlist.
Here is a illustrative Example of How the Synthesis Maps the Gate-level-Netlist:
- Download Dependencies for Yosys
$ sudo apt install -y clang bison flex \
libreadline-dev gawk tcl-dev libffi-dev git \
graphviz xdot pkg-config python3 libboost-system-dev \
libboost-python-dev libboost-filesystem-dev zlib1g-dev
- Clone the Repo
$ git clone https://github.com/YosysHQ/yosys.git - Now To Install
$ cd yosys
$ make
$ sudo make install
Now Run cd into /usr/bin and do:sudo ln -s /home/user/yosys-dir/yosys yosys
-
OpenROAD is an integrated chip physical design tool that takes a design from synthesized Verilog to routed layout.
-
An outline of steps used to build a chip using OpenROAD is shown below:
- Initialize floorplan - define the chip size and cell rows
- Place pins (for designs without pads )
- Place macro cells (RAMs, embedded macros)
- Insert substrate tap cells
- Insert power distribution network
- Macro Placement of macro cells
- Global placement of standard cells
- Repair max slew, max capacitance, and max fanout violations and long wires
- Clock tree synthesis
- Optimize setup/hold timing
- Insert fill cells
- Global routing (route guides for detailed routing)
- Antenna repair
- Detailed routing
- Parasitic extraction
- Static timing analysis
-
Before Installing openROAD lemon needs to be instal First https://lemon.cs.elte.hu/trac/lemon/wiki/Downloads.
cd
git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD.git
cd OpenROAD
sudo ./etc/DependencyInstaller.sh
cd
git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts
cd OpenROAD-flow-scripts
./build_openroad.sh –local
export OPENROAD=~/OpenROAD-flow-scripts/tools/OpenROAD
export PATH=/home/vinayreddy/OpenROAD-flow-scripts/tools/install/OpenROAD/bin:/home/vinayreddy/OpenROAD-flow-scripts/tools/install/yosys/bin:/home/vinayreddy/OpenROAD-flow-scripts/tools/install/LSOracle/bin:$PATH
- Will Perform a RTL2GDSII flow of a ibex(RISC-V Proccessor)
cd OpenROAD-flow-scripts
cd flow
make DESIGN_CONFIG=./designs/sky130hd/ibex/config.mk
- After Completing the Flow the GDS,SDC files are Extracted in Location
../OpenROAD-flow-scripts/flow/results/sky130hd/ibex/base/6_final.gds.
- Set the
sky130Apath in file called platform_config.json that is insideOpenFASOC/openfasoc/common/directory. By default, the file will have the following entries.
-
Introduction to howing of Temperature Sensor Generation using OpenFASOC.
-
The Temperature Sensor Generated is a Mixed-Signal Based On the paper.
Citation: Q. Zhang et al., "An Open-Source and Autonomous Temperature Sensor Generator Verified With 64 Instances in SkyWater 130 nm for Comprehensive Design Space Exploration," in IEEE Solid-State Circuits Letters, vol. 5, pp. 174-177, 2022, doi: 10.1109/LSSC.2022.3188925. -
It consists of a ring oscillator whose frequency is controlled by the voltage drop over a MOSFET operating in subthreshold regime, where its dependency on temperature is exponential.
-
The physical implementation of the analog blocks in the circuit is done using two manually designed standard cells:
- HEADER cell, containing the transistors in subthreshold operation;
- SLC cell, containing the Split-Control Level Converter.
-
The gds and lef files of HEADER and SLC cells are pre-created before the start of the Generator flow.
-
The layout of the HEADER cell,SLC Cell is shown below:
- To run the default generator, cd into
~/openfasoc/generators/temp_senseand usemake sky130hd_tempIf a PDK_ROOT error arises, then provide PDK_ROOT before running the above exportPDK_ROOT=/usr/local/share/pdk.If OpenROAD not found in path error arises, provide path to openROAD along with PDK_ROOT.
export OPENROAD=~/OpenROAD-flow-scripts/tools/OpenROAD/
export PATH=/home/rahul/OpenROAD-flow-scripts/tools/install/OpenROAD/bin:/home/rahul/OpenROAD-flow-scripts/tools/install/yosys/bin:/home/rahul/OpenROAD-flow-scripts/tools/install/LSOracle/bin:$PATH
-
The default circuit’s physical design generation can be divided into three parts:
- Verilog generation(:heavy_check_mark:)
- RTL-to-GDS flow (OpenROAD)(:heavy_check_mark:)
- Post-layout verification (DRC and LVS)(:heavy_check_mark:)
-
After a successful run the following message is displayed
- To run verilog generation, type the command
make sky130hd_temp_verilog
- Type the Command
make sky130hd_temp
- Synthesis is Performed by yosys.The systhesis verilog codes in
/openfasoc/openfasoc/generators/temp-sense-gen/flow/results/sky130hd/tempsense
- The floorplan for the physical design is generated with OpenROAD, which requires a description of the power delivery network in
pdn.cfg.
- Placement takes place after the floorplan is ready and has two phases: global placement and detailed placement. The output of this phase will have all
instances placed in their corresponding voltage domain, ready for routing.
- Routing is also divided into two phases: global routing and detailed routing. Right before global routing, OpenFASoC calls
/openfasoc/openfasoc/generators/temp-sense-gen/flow/scripts/openfasocpre_global_route.tcl:
| SI.No | Action Item | Status |
|---|---|---|
| 1 | Pre-layout Analysis Three-Stage Ring-Oscillator | ✔️ |
| 2 | Post-Layout Analysis of Ring-Oscillator Using Magic | ✔️ |
| 3 | Post-layout Analysis of Ring-Oscillator Using Align | ✔️ |
| 4 | Design of 4-bit Counter Verilog Blocks |
- A ring oscillator is a self-toggling circuit that generates clock-like pulses without any external input, other than the power that it needs.Here a 3 staged Cascaded inverter B2B.
- This Circuit Generates the Following Netlist: ring_os.spice
- The Test Circuit for ring oscillator
- Manual Layout of a Three-Stage Ring Oscillator
- You can Find the Netlist Here: ring_osc2.spice
- First Lets Modify the Generated Netlist from Xchem in the Following Way:
.subckt ring_osc2 OUT VDD GND
XM1 net1 OUT GND GND sky130_fd_pr__nfet_01v8 L=150e-09 w=10.5e-7 nf=10 m=1
XM2 net2 net1 GND GND sky130_fd_pr__nfet_01v8 L=150e-09 w=10.5e-7 nf=10 m=1
XM3 OUT net2 GND GND sky130_fd_pr__nfet_01v8 L=150e-09 w=10.5e-7 nf=10 m=1
XM4 net1 OUT VDD VDD sky130_fd_pr__pfet_01v8 L=150e-09 w=10.5e-7 nf=10 m=1
XM5 net2 net1 VDD VDD sky130_fd_pr__pfet_01v8 L=150e-09 w=10.5e-7 nf=10 m=1
XM6 OUT net2 VDD VDD sky130_fd_pr__pfet_01v8 L=150e-09 w=10.5e-7 nf=10 m=1
.ends ring_osc2
.subckt ring_oscillator_stage vi vo vssx vccx vctl
mp0 vo vi vctl vccx sky130_fd_pr__pfet_01v8 L=150e-9 W=420e-9 nf=2
mn0 vo vi vssx vssx sky130_fd_pr__nfet_01v8 L=150e-9 W=420e-9 nf=2
.ends
.subckt ring_oscillator vctl vo vccx vssx
xi0 vo n1 vssx vccx vctl ring_oscillator_stage
xi1 n1 n2 vssx vccx vctl ring_oscillator_stage
xi2 n2 n3 vssx vccx vctl ring_oscillator_stage
xi3 n3 n4 vssx vccx vctl ring_oscillator_stage
xi4 n4 vo vssx vccx vctl ring_oscillator_stage
.ends
- Refer The Examples Here -ring_oscillator.sp
- Now You Can Run ALIGN to Generate the Layout
- Open the GDS In Magic
- The Extracted Netlist from Magic : RING_OSC2_0.spice
- Pre-layout Ring-Oscillator and Post-layout Ring-Oscillator with Align have matched.
| SINO. | Action Item | Status |
|---|---|---|
| 1 | Ring Oscillator Pre-layout Analysis | ✔️ |
| 2 | Ring Oscillator Post-layout Analysis Using ALIGN | ✔️ |
| 3 | Comparator Circuit Pre-Layout Analysis | ✔️ |
| 4 | Design of a 1-bit ADC Blocks | ✔️ |
| 5 | Comparator Circuit Post-layout Using ALIGN | ✔️ |
| 6 | Comparsion of Pre-layout vs Post Layout of Analog BLocks using ALIGN | ✔️.. |
| 7 | One-bit Comparator Post-layout Analysis | ✔️ |
| 8 | Dummy Verilog Codes for Analog Blocks | ✔️ |
The RO design Last Week is Not Compatable with the Comparator(Block) As the RO Frequency is High.So,By increasing the Width,Length Across the circuit the tpd of Unit Inverter is Increased.Hence Decresing the Oscillating Frequency.
!
- Prelayout Transient Analysis
- Here is the Spice .sp netlist for RO : ring_osc1.sp
- Here is the 1-bit Comparator Circuit:
- Here is the .sp netlist for Comparator Circuit: comparator.sp
- Analysis of Delay Time and Frequency of Ring Oscillator
- Analysis of VTC Characteristics of Comparator
- Error with Generating Resistor Bridge with Align
- Tring to Figure out or Attaching Manually
- 1-bit ADC code Click Here.
1-bit ADC
module async_counter(
input wire v_bias,
input wire v_inn,
output wire out_bit
);
wire ring_Fout;
RING_OSCILLATOR RING_OSCILLATOR(
.INP(ring_Fout)
);
COMPARATOR COMPARATOR(
.INP(ring_Fout),
.INN(v_inn),
.BIAS(v_bias),
.OUT(out_bit)
);
endmodule
Comparator
module COMPARATOR(
input INP,
input INN,
input BIAS,
output OUT
);
endmodule
Ring-Oscillator
module RING_OSCILLATOR(
output INP
);
endmodule
- As will Have Already ran few Designs in Week-5,6.Its Time to Set-up our own file for Design.
- The File is Located and Having Folder As Follows;
- Take the Analog Blocks Generated In the Previous week to Generate the Asynchronous Counter.
- But Before Using ALIGN generated Blocks in OpenFASOC make Sure you Do Pin Configuration else the Blocks will no be Routed(Placed) in the Design.
- Refer Lef & Gds For OpenFASoC Flow
- Now First Lets Configure the Blocks.
- Place the Gds,Lef Files You Generated by Naming the folder as Platform Name.
- The pdn.tcl refers to Power Disturbution Network which has The Detials of Placeing Power Port and Metals to be Used for the Design.
- Now Moving to the Most Critical part of the Design Flow Folder.
- Design Folder Consists of Files
- src consists of Dummy Verilog/Verilog Files for the Design.
- Config.mk File Have the Following Attributes.
- Now Configure the Makefile to run the Flow.
- Other Files like logs,results,utils,report are Generated by OpenFASOC.
- Srcipts consist the Flow for running the Flow In various Stages of the Flow.
- Make All Necessary Changes in the Files and To Run complete Flow Use
make sky130hd_verilogandmake sky130hd_build - Or to Run the Flow Interactively refer Make Interactively.
- Verilog Generation.
- Synthesis
- floorplanning
- Place
- Route
- Now Add
manual_macros.tclin blocks Folder
- Add the Line
29-30to place the Blocks
- where
MACRO_PLACE_HALOdefines the Space Between the Macros. - And
MARCO_PLACE_CHANNELdefines Wiring Space. - And the Macro placement TCL files
- Counter Circuit RTL file and Test bench
ud_counter.v
module ud_counter (input clk,
input rstn,
output reg [3:0] out);
wire [3:0] cnt;
tff t0(.clk(clk),.rstn(rstn),.t(1'b1),.q(cnt[0]));
tff t1(.clk(cnt[0]),.rstn(rstn),.t(1'b1),.q(cnt[1]));
tff t2(.clk(cnt[1]),.rstn(rstn),.t(1'b1),.q(cnt[2]));
tff t3(.clk(cnt[2]),.rstn(rstn),.t(1'b1),.q(cnt[3]));
always@*
begin
out<=cnt;
end
endmodule
module tff(input clk,input rstn,input t,output reg q);
always @ (negedge clk)begin
if(!rstn)
q<=0;
else
if(t)
q<=~q;
else
q<=q;
end
endmodule
tb_counter.v
`timescale 1ns/1ps
module tb_counter();
reg clk,rstn;
wire [3:0]out;
ud_counter c0(clk,rstn,out);
always #5 clk=~clk;
initial
begin
$dumpfile("tb_counter.vcd");
$dumpvars(0,tb_counter);
end
initial begin
clk<=0;
rstn<=0;
#20 rstn<=1;
#150 rstn<=0;
#50 rstn<=1;
#200$finish;
end
endmodule
| SI | Action Item | Status |
|---|---|---|
| 1 | Pre-Layout Analysis of Two-Bit ADC(Course) | ✔️ |
| 2 | Post-layout Analysis of Two-bit ADC(Course) | ✔️ |
| 3 | Pre-layout Analysis of Sample and Hold Circuit | ✔️ |
| 4 | Post-layout Analysis of Sample and Hold Circuit | ✔️ |
| 5 | Pre-layout Analysis of 2-bit DAC Circuit | ✔️ |
| 6 | Postlayout Analysis of 2-bit DAC Circuit | ✔️ |
| 7 | Residue Amplifier Circuit | ✔️ |
| 8 | Post-Layout Residue Amplifier Circuit | ✔️ |
- To Design a Subranging ADC we Neea the Following Blocks.
- (Note:The DAC block Should be 4 bit Accurate).
- Fine ADC With More Accurate Resolution.
- Design Spec to Consider.
-
Analog-Digital Converter Consists of a 3-Comparator Circuits and Resistive Bridge.
-
The Output of the ADC Analog Block is As Follows.
-
2 bit Flash ADC:
input Voltage C3C2C1 b1b0 0<Vin<Vref/4 000 00 Vref/4<Vin<Vref/2 001 01 Verf/2<Vin<Vref 011 10 Vref<Vin 111 11 
- Here is the
Twobit_Flash_ADC.sp:
| GDS File | Lef file |
|---|---|
 |
 |
- Extracted Netlist From Magic After Modification.
- Facing Error With C2,C3 Signal.
- This Raised Due to Prasitics in the Layout.Which are minimising the Frequency of Operation.(1Ghz,Max-600MHz)
| Prelayout - At 100Mhz | Postlayout -At 100MHz |
|---|---|
 |
 |
- This Chractristics then the Standard one avsddac_3v3_sky130_v2.
| GDS File | Lef file |
|---|---|
 |
 |
- Some Glitch with Prasitics.
| Connects Ports | Power Ports |
|---|---|
 |
 |
- There Still Some Issue with a Port at Layout
- Two Bit ADC:
- Delay,Rise Time,Fall Time.
- DAC Resolution,settling Time,Overshoots(INL,DNL).
- Connecting Resistors with References ❌
| SI No. | Action Item | Status |
|---|---|---|
| 1 | Two-Bit ADC with Resistor Bridge Uisng ALIGN | ✔️ |
| 2 | Two-Bit DAC with Resistor Bridge Using ALIGN | ✔️ |
| 3 | Subtractor and Residue Amplifier Circuit using ALIGN | ✔️ |
| 4 | Sample and Hold Circuit Using Align | :Heavy_check_mark: |
| 5 | Two-Bit ADC using OpenFASOC | :Heavy_check_mark: |
| 6 | Two-Bit ADC + DAC interfacing using OpenFASOC | ⭕ |
- To Generated the Layout of Two-bit Align.
- With Capacitor to be Replaced with Resistors.
| GDS File | Lef file |
|---|---|
 |
 |
- Replacing Caps with Resistor in
.python.gdsfile.
- After Placing Pins the Extracted Netlist is :
- The Postlayout Analysis of ADC with Resistive Brigde.
- Error with Extrating The Precise value of Resistor from GDS file.
| GDS File | Lef file |
|---|---|
 |
 |
- replacing Caps with Resistors
