JohnVida

JohnVida's Stars

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3.1k167176752

• google/skywater-pdk

  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

  Language:Python3k154272390

• godlygeek/tabular

  Vim script for text filtering and alignment

  Language:Vim Script2.6k6255164

• lowRISC/opentitan

  OpenTitan: Open source silicon root of trust

  Language:SystemVerilog2.6k1076.8k764

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.1k9440285

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.6k601378

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.1k39120262

• pulp-platform/common_cells

  Common SystemVerilog components

  Language:SystemVerilog5041957145

• ZipCPU/wb2axip

  Bus bridges and other odds and ends

  Language:Verilog4843152101

• vhda/verilog_systemverilog.vim

  Verilog/SystemVerilog Syntax and Omni-completion

  Language:Vim Script3673214189

• hemantapkh/TorrentHunt

  🏴‍☠️ The ultimate torrent bot on telegram

  Language:Python31389119

• Xilinx/systemctlm-cosim-demo

  QEMU libsystemctlm-soc co-simulation demos.

  Language:C++127193146

• agra-uni-bremen/crave

  Constrained random stimuli generation for C++ and SystemC

  Language:C++49141113

• Practical-UVM-Step-By-Step/Practical-UVM-IEEE-Edition

  This is the repository for the IEEE version of the book

  Language:Verilog494136

• westerndigitalcorporation/DiskSim

  Language:C459033

• systemc/uvmc

  Connecting SystemC with SystemVerilog

  Language:C++364017

• leds-lab/redscarf

  System-on-Chip Interconnection Network - Simulation Environment (front-end)

  Language:C++14320

• Baungarten-CINVESTAV/AI_by_AI

  AI by AI

  Language:Verilog101

• snps-virtualprototyping/ocx-qemu-arm

  OpenCpuX wrapper for a Unicorn/QEMU ARM core ISS

  Language:C++8145

• masc-ucsc/MASC-AI-Synthesized-Cryptoprocessor

  Language:Verilog6400

• BoChen-Ye/OpenSoCFabric

  OpenSoC Fabric - A Network-On-Chip Generator

  Language:Scala4000

• noritsuna/Edge_Circuit_Designer

  This repository is for 2nd AI Generated Design Contest.

  Language:Verilog300

• MDH-BUMBLE/PSS

  PSS Blended Modeling

  Language:Java2103

• amiq-consulting/accellera-fc4sc

  Functional Coverage for SystemC (FC4SC) library which provides mechanisms for functional coverage definition, collection and reporting.

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