HEEPsilon is a versatile computing platform targeting ultra low power processing of biological and environmental signals. It is built over the X-HEEP platform and extends it with openEdgeCGRA a design-time resizable and run-time reprogrammable Coarse Grained Reconfigurable Array (CGRA). For a brief insight on HEEPsilon please refer to our abstract:
📄 An Open-Hardware Coarse-Grained Reconfigurable Array for Edge Computing.
As an X-HEEP spinoff, HEEPsilon keeps all X-HEEP functionalities, from RTL simulation on Verilator, VCS and Questasim to implementation on the PYNQ-Z2 FPGA. Our cousin HEEPocrates was recently taped-out in TSMC 65nm process and is currently undertaking tests successfully.
In addition to all the tools available for X-HEEP, HEEPsilon is building a toolchain to simplify the C-code→CGRA process.
Due to its modular design, HEEPsilon respects the X-HEEP workflow. As such, you can follow X-HEEP's getting started to set up the environment... HOWEVER...
Althought the HEEPsilon team will try to keep the latest version of X-HEEP available, changes in the X-HEEP setup might not reflect immediately on this repository.
👉 For the most accurate set-up instructions please refer to the documentation of the vendorized X-HEEP.
The CGRA used in HEEPsilon can be simulated with CGRA-instruction accuracy using the ESL-CGRA simulator. This allows for fast and easy-to-debug design of kernels for the CGRA. Once you are happy with your design you can compile the assembly and get the bitstream to load into the CGRA.
Your kernel is too complex to be mapped manually? Try using the SAT-MapIt mapper and compiler. Properly label your C-code and let SAT-MapIt find an efficient mapping you can test in the simulator and deploy in the CGRA.
Once you have tested your setup with the cgra_func_test application you can start trying out different kernels. HEEPsilon provides a set of tools to easily go from C-code to CGRA bitstreams. All kernels are converted into a standard C source and header file pair which you can use with the kernel_test application to measure the speed-up of your CGRA implementation as well as see stochastical variations.
If you application requires some hardcore input-output management, maybe you want to try out the X-HEEP FEMU. Connect your PYNQ-Z2 FPGA via SSH and start deploying different hardware versions of X-HEEP or HEEPsilon, test different software applications and interface with the hardware from the comfort of Python scripts or Jupyter notebooks.
HEEPsilon is a newborn project that already brings together dozens of researchers from 4 universities across Switzerland, Spain and Italy. There is plenty of cool work to be done for and with HEEPsilon, join us!
Pending work includes:
- Development of new kernels for the CGRA and validation in real applications.
- Integration of the different compilation tools into a single workflow.
- Extracting variable information from the LLVM pass during C-code → CGRA assembly process.
- Characterizing the CGRA hardware for cycle and energy-accurate simulation.
Have some questions? Don't hesitate to contact us: juan.sapriza@epfl.ch