Pinned Repositories
30-Days-Of-Python
30 days of Python programming challenge is a step-by-step guide to learn the Python programming language in 30 days. This challenge may take more than100 days, follow your own pace.
ahb2apb-bridge
An uvm verification env for ahb2apb bridge
AMBA_APB_SRAM
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
apb-uart-uvm-env
Awesome-ChatGPT-prompts-ZH_CN
如何将ChatGPT调教成一只猫娘
basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
FPGA
数字IC相关资料
INT_FP_MAC
INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
isp
camera pipeline
opentitan
OpenTitan: Open source silicon root of trust
JunminHe's Repositories
JunminHe/FPGA
数字IC相关资料
JunminHe/INT_FP_MAC
INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
JunminHe/30-Days-Of-Python
30 days of Python programming challenge is a step-by-step guide to learn the Python programming language in 30 days. This challenge may take more than100 days, follow your own pace.
JunminHe/ahb2apb-bridge
An uvm verification env for ahb2apb bridge
JunminHe/AMBA_APB_SRAM
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
JunminHe/apb-uart-uvm-env
JunminHe/Awesome-ChatGPT-prompts-ZH_CN
如何将ChatGPT调教成一只猫娘
JunminHe/basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
JunminHe/isp
camera pipeline
JunminHe/opentitan
OpenTitan: Open source silicon root of trust
JunminHe/perl5
🐫 The Perl programming language
JunminHe/Practical-UVM-IEEE-Edition
This is the repository for the IEEE version of the book
JunminHe/pyuvm
The UVM written in Python
JunminHe/Verification_Digital_Systems
Verification of Digital Systems (EE382M)
JunminHe/verilog-basic
learn the combinational and sequential logic circuit.
JunminHe/verilog-pipeline-processor
RISC V pipeline processor in verilog