JunminHe

JunminHe's Stars

• tensorflow/tensor2tensor

  Library of deep learning models and datasets designed to make deep learning more accessible and accelerate ML research.

  Language:Python15.6k3.5k

• xai-org/grok-1

  Grok open release

  Language:Python49.6k8.3k

• meta-llama/PurpleLlama

  Set of tools to assess and improve LLM security.

  Language:Python2.7k453

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.7k380

• microease/Renzhengfeiwenji

  任正非文集

  21248

• L1Xu4n/Awesome-ChatGPT-prompts-ZH_CN

  如何将ChatGPT调教成一只猫娘

  2.8k159

• subbdue/systemverilog.io

  Code used in

  Language:SystemVerilog17529

• bxinquan/zynqmp_cam_isp_demo

  ISP-Lite, VIP, MIPI-RX IP实现，测试平台为KV260+AR1335 3MP@30fps

  Language:VHDL8533

• jhfmat/zynq_cam_isp_demo

  基于verilog实现了ISP图像处理IP

  42

• bxinquan/zynq_cam_isp_demo

  基于verilog实现了ISP图像处理IP

  Language:VHDL23178

• Sparky-Xia/THU-Mathematics-Books

  清华数学系部分课程教材及参考资料，自用，侵删

  22360

• ucb-bar/chisel-tutorial

  chisel tutorial exercises and answers

  Language:Scala697197

• ucb-bar/chiseltest

  The batteries-included testing and formal verification library for Chisel-based RTL designs.

  Language:Scala22476

• ucb-bar/gemmini

  Berkeley's Spatial Array Generator

  Language:Scala822173

• mushfiqulalam/isp

  camera pipeline

  Language:Python348126

• lizhirui/DreamCore

  Language:C++633

• XUANTIE-RV/wujian100_open

  IC design and development should be faster，simpler and more reliable

  Language:Verilog1.9k573

• JunminHe/INT_FP_MAC

  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

  11

• wavedrom/wavedrom.github.io

  Digital timing diagram editor

  Language:JavaScript944161

• lucky-wfw/The-project-of-Verilog

  Some design examples of Verilog about digital circuits

  Language:Verilog236

• lucky-wfw/ARM_AMBA_Design

  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

  Language:Verilog11134

• OpenEDF/verilog-basic

  learn the combinational and sequential logic circuit.

  Language:SystemVerilog111

• JunminHe/FPGA

  数字IC相关资料

  11

• pyuvm/pyuvm

  The UVM written in Python

  Language:Python37971

• courageheart/AMBA_APB_SRAM

  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

  Language:SystemVerilog15861

• Lampro-Mellon/apb-uart-uvm-env

  Language:SystemVerilog3413

• Perl/perl5

  🐪 The Perl programming language

  Language:Perl2k559

• lowRISC/opentitan

  OpenTitan: Open source silicon root of trust

  Language:SystemVerilog2.6k783

• chipsalliance/Cores-VeeR-EH1

  VeeR EH1 core

  Language:SystemVerilog826220

• Verdvana/Wireless_Transmission_Quality_Detection

  基于CC2530的ZigBee协议无线传输质量监测系统（互相收发）

  2