Jusan-zyh

Pinned Repositories

cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Language:Python00
dataease
人人可用的开源数据可视化分析工具。
Language:Java00
DDR4MemoryController
HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
Language:SystemVerilog00
dma_ip_drivers
Language:C0 0 00
FreeRDP
FreeRDP is a free remote desktop protocol library and clients
Language:C00
FreeRDP-WebConnect
A gateway for seamless access to your RDP-Sessions in any HTML5-compliant browser
Language:C++0 0 00
git
Git Source Code Mirror - This is a publish-only repository but pull requests can be turned into patches to the mailing list via GitGitGadget (https://gitgitgadget.github.io/). Please follow Documentation/SubmittingPatches procedure for any of your improvements.
Language:C00
gtkwave
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
Language:C00
hello-world
just another repository
00
iverilog
Icarus Verilog
Language:C++00

Jusan-zyh's Repositories

Jusan-zyh/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Language:Python00
Jusan-zyh/dataease
人人可用的开源数据可视化分析工具。
Language:Java00
Jusan-zyh/dma_ip_drivers
Language:C0 0 00
Jusan-zyh/FreeRDP
FreeRDP is a free remote desktop protocol library and clients
Language:C00
Jusan-zyh/FreeRDP-WebConnect
A gateway for seamless access to your RDP-Sessions in any HTML5-compliant browser
Language:C++0 0 00
Jusan-zyh/git
Git Source Code Mirror - This is a publish-only repository but pull requests can be turned into patches to the mailing list via GitGitGadget (https://gitgitgadget.github.io/). Please follow Documentation/SubmittingPatches procedure for any of your improvements.
Language:C00
Jusan-zyh/gtkwave
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
Language:C00
Jusan-zyh/iverilog
Icarus Verilog
Language:C++00
Jusan-zyh/JNIDemo
a JNIDemo for zyh
Language:C1 0
Jusan-zyh/Jusan-zyh.github.io
hexo个人博客
Language:HTML1 0
Jusan-zyh/learngit
0 0
Jusan-zyh/litejesd204b
Small footprint and configurable JESD204B core
Jusan-zyh/litescope
Small footprint and configurable embedded FPGA logic analyzer
Jusan-zyh/litex
Build your hardware, easily!
Jusan-zyh/marktext
📝A simple and elegant markdown editor, available for Linux, macOS and Windows.
Jusan-zyh/milkdown
🍼 Plugin driven WYSIWYG markdown editor framework.
Jusan-zyh/mygitremote
Jusan-zyh/myhdl
The MyHDL development repository
Jusan-zyh/OpenMMLabCourse
OpenMMLab course index and materials
Language:Jupyter Notebook0 0
Jusan-zyh/pcie_analyzer
PCIe analyzer experiments
Language:Python0 0
Jusan-zyh/Quasar
Remote Administration Tool for Windows
Jusan-zyh/QWidgetExe2
Qt编写的一些项目的可执行文件，包括对应的说明文档、运行截图等，项目都是商业级别，如有需要完整源码或者定制功能请联系购买，QQ：517216493 微信：feiyangqingyun 推荐加微信。
Jusan-zyh/remote-desktop-control
远程桌面控制(Spring+Netty+Swing)
Language:Java0 0
Jusan-zyh/rustdesk
Open source virtual / remote desktop infrastructure for everyone! The open source TeamViewer alternative. Display and control your PC and Android devices from anywhere at anytime.
Jusan-zyh/sumatrapdf
SumatraPDF reader
Jusan-zyh/Verilog_UDP_TCP
Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.
Language:Verilog0 0
Jusan-zyh/wb2axi
Wishbone to ARM AMBA 4 AXI
Jusan-zyh/xmake
🔥 A cross-platform build utility based on Lua
Jusan-zyh/zqh_riscv
zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this project Now it's focusing on Embedded system
Jusan-zyh/zyh
short for name
Language:C0 0