I am Shashank Sirohiya, a VLSI enthusiast and this is my journey of 100 days of RTL(Verilog, System verilog, UVM).I mostly use Questasim software for the simulation of RTL Codes and the Synthesis is performed by using Xilinx Vivado Design Suite.
--------------------------------------------// Day:1 _"ALU"
Day:2 _"Binary_to_Gray_Decoder"
Day:3 _"Gray_to_Binary_Decoder"
Day:4 _"3_8Decoder"
Day:5 _"8_3Encoder"
Day:6 _"Parity_Encoder"
Day:7 _"Priority_Encoder"
Day:8 _"Binary_to_Bcd"
Day:9 _"Bcd_to_7Segment"
Day:10_"Parameterized_full_adder"
Day:11_"Carry_Look_Ahead_Adder"
Day:12_"Full_Subtractor"
Day:13_"Multiplier"
Day:14_"Divider"
Day:15_"Comparator"
Day:16_"Multiplexer"
Day:17_"Demultiplexer"
Day:18_"Endianess"
Day:19_"Inter_Intra_Delay"
Day:20_"Booth algorithm"
Day:21_"D_Latch"
Day:22_"SR_Latch"
Day:23_"D_FF"
Day:24_"JK_FF"
--------------------------------------------//
Day:25_"Mod7_Counter"
Day:26_"Gray_Counter"
Day:27_"Ring_Counter"
Day:28_"Jhonson_Counter"
Day:29_"Synchronous_Counter"
Day:30_"Universal_Binary_Counter"
Day:31_"FSM_Onehot"
Day:32_"Sequence_Detector_10110"
Day:33_"FSM_Traffic_Light_Controller"
Day:34_"FSM_Sequence_Generator"
--------------------------------------------//
Day:35_"LFSR"
Day:36_"RSB"
Day:37_"SISO"
Day:38_"SIPO"
Day:39_"PISO"
Day:40_"PIPO"
Day:41_"Universal_Shift_Register"
Day:42_"Parameterised_Register"
Day:43_"Barrel_Shift_Registor"
Day:44_"FIFO_Synchronous"
Day:45_"15_15Rom"
Day:46_"Asynchronous_Rom"
Day:47_"Rom_Using_Case"
Day:48_"Rom_Alu_Decoder"
Day:49_"Synchronous_Ram"
Day:50_"16_16Ram"
Day:51_"Asynchronous_Ram"
Day:52_"Ram_8191k"
Day:53_"Parameterised_Ram"
Day:54_"Pipeline_shift"
Day:55_"Delays"
Day:56_"Clk_phase"
Day:57_"Frequency_Divider_by_Oddnumber"
Day:58_"Frequency_Divider_by_Even_number"
--------------------------------------------//
Day:59_"Priority_resolver"
Day:60_"Psuedo_Random_Sequence"
Day:61_"Parameterised_Cube"
Day:62_"Password(Digital Safe locker)"
Day:63_"Prime_Number"
Day:64_"Elevator"
Day:65_"Vending_Machine"
Day:66_"Rail_Track"
Day:67_"Running_Led"
Day:68_"Palindrome_of_a_number"
Day:69_"Data_Encryption"
Day:70_"Data_Decryption"
------------------SV--------------------------//
Day:71_"Randomization"
Day:72_"Pre - Post Randomization"
Day:73_"Inline Constraints"
Day:74_"Weighted Constraints"
Day:75_"Inside Operator"
Day:76_"Oops Inheritance"
Day:77_"Oops Encapsulation"
Day:78_"Oops Polymorphism"
Day:79_"Mailbox"
Day:80_"Fixed & Dynamic Array"
Day:81_"Enum Data type"
Day:82_"Package in SV"
Day:83_"Semaphore"
Day:84_"Functional Coverage | Implicit bin"
Day:85_"Functional Coverage | Explicit bin"
--------------------UVM------------------------//
Day:86_"UVM_MACROS"
Day:87_"Working with Verbosity level and ID"
Day:88_"UVM_FIELD_MACROS_int"
Day:89_"UVM_FIELD_MACROS_enum"
Day:90_"UVM_FIELD_MACROS_arrays"
Day:91_"UVM_FIELD_MACROS_copy and clone"
Day:92_"UVM_FIELD_MACROS_shallow and deep copy"
--------------------------------------------//
Day:93_"SV_TB_DFF"
Day:94_"SV_TB_FIFO"
Day:95_"SV_TB_ADDER"
Day:96_"UVM_TB_ADDER"
--------------------------------------------//
Day:97_"AXI4_LITE"
Day:98_"AXI"
Day:99_"APB"
Day:100_"AHB"
--------------------------------------------//
Next_upcoming_"SPI""UART""I2C"
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