Khalique13
Khalique is Application Engineer at Cadence Design Systems, completed Bachelor of Technology in ECE, he is focused on Microelectronics and VLSI.
https://github.com/CadenceNoida
Pinned Repositories
6t_sram_cell
Design of 6T SRAM Cell using SkyWater 130nm technology.
99days_of_rtl_code
avsddac_3v3_sky130_v2
BandgapIP_Design_VSDOpen21_Workshop
caravel_vsd_priority_encoder
https://caravel-user-project.readthedocs.io
dvsd_pe_sky130
This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral RTL of an 8-bit Priority Encoder, using SkyWater 130 nm PDK.
Exclusive_OR_gate
PLL_OSU180_Workshop
On-Chip Clock Multiplier (PLL) on OSU180 Workshop
skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
Khalique13's Repositories
Khalique13/dvsd_pe_sky130
This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral RTL of an 8-bit Priority Encoder, using SkyWater 130 nm PDK.
Khalique13/6t_sram_cell
Design of 6T SRAM Cell using SkyWater 130nm technology.
Khalique13/vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
Khalique13/caravel_vsd_priority_encoder
https://caravel-user-project.readthedocs.io
Khalique13/99days_of_rtl_code
Khalique13/avsddac_3v3_sky130_v2
Khalique13/BandgapIP_Design_VSDOpen21_Workshop
Khalique13/Exclusive_OR_gate
Khalique13/PLL_OSU180_Workshop
On-Chip Clock Multiplier (PLL) on OSU180 Workshop
Khalique13/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Khalique13/FPGA_VSDOpen21_Workshop
Digital Design on FPGA VSDOpen21 Workshop
Khalique13/gate_level_simulation
Khalique13/github-slideshow
A robot powered training repository :robot:
Khalique13/magic
Magic VLSI Layout Tool
Khalique13/skywater-pdk-parser
Khalique13/test
Khalique13/VSD-IAT-Workshop-Github-Repos
GitHub is the new Resume for VLSI industry GitHub is indeed the new RESUME for VLSI industry. Really, if you are recruiting person and looking forward to judge a new candidate for a role in company, ask for GitHub project link. Projects written on resume and projects available on GitHub by a candidate will immediately give you an idea about his/her perseverance, dedication, sincerity, productivity and amount of hard-work he/she can put inside a project.