Digital Design on FPGA VSDOpen21 Workshop

Introduction
Benefits
Verilog
Makerchip
Interfacing LEDs
Seven Segment Display
4-way Traffic Light Controller
Finite State Machines
Traffic Light Controller Lab
References
Author
Acknowledgement

Introduction

FPGA also known as Field-Programmable Gate Array, is a hardware circuit board that executes hardware models. It is used for prototyping ASICs and Processors. This workshop is to learn and understand Digital Design using Virtual FPGA.

Benefits of Virtual FPGA

Virtual demo FPGA visualizations
Access to various kinds of Board
Debug each & every cycle
Open-source (Freely access to all)

The detailed information on Virtual FPGA Lab can be found here

Verilog

Hardware Description Language
Verification
- Simulation
- Timing Analysis
- Test Analsis
- Synthesis
Level of Abstraction
- Behavioural Level
- Register-Transfer Level
- Gate Level

Makerchip

Makerchip is a free IDE which is used to develop Integrated Circuits, where you can design, compile, and simulate hardware using verilog all from your browser. It is available as https://makerchip.com/.

Interfacing LEDs

Assigning random values to the LEDs

LED Binary Counter

Interfacing LED Lab

Seven Segment Display

Design of Seven-Segment Display

Interfacing Seven Segment Display

Interfacing Seven Segment Display lab

4-way Traffic Light Controller

Problem Statement

Finite State Machines

Abstract model of computation that is used to model logic
Based on the current state and a given input the machine performs state transitions and produces outputs.
Two basic types are Mealy and Moore mahines

Verilog Code for NORTH, SOUTH, EAST and WEST

NORTH :
                    begin                      
                       // Enable first seven segment and set to Green 
                       digit <= 4'b0111;
                       segment <= 7'b1110111;
                        /* TODO: 1. Keep the green NORTH signal active for 8 seconds 
                                2. Set state of signal to yellow NORTH after that 
                          HINT: Use if-else block
                        */
                       if(count==7) begin
                             assign state=NORTH_Y;
                        	  assign count=0;    
                          end
                       else assign count=count+1;   
                    end

Verilog Code for NORTH_Y, SOUTH_Y, EAST_Y and WEST_Y

NORTH_Y :
                    begin
                        // Enable first seven segment and set to Yellow
                        digit <= 4'b0111;
                        segment <= 7'b1111110;
                        /* TODO: 1. Keep the yellow NORTH signal active for 4 seconds 
                                2. Set state of signal to green SOUTH after that 
                        */
                      if(count==3) begin
                             assign state=SOUTH;
                        	  assign count=0;    
                          end
                       else assign count=count+1;
							end

Khalique13/FPGA_VSDOpen21_Workshop