Kumonda221-CrO3

Kumonda221-CrO3's Stars

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.1k268

• RV-BOSC/OpenNoC

  Language:Verilog668

• ccfddl/ccf-deadlines

  ⏰ Collaboratively track deadlines of conferences recommended by CCF (Website, Python Cli, Wechat Applet) / If you find it useful, please star this project, thanks~

  Language:Vue6.5k447

• ben-marshall/verilog-vcd-parser

  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

  Language:C++9036

• Tang-Haojin/YuQuan

  A RISC-V core running Debian (and a LoongArch core running Linux).

  Language:Scala224

• dujingning/inicpp

  The INI header-only library for Modern C++ supports reading and writing, even writing comments. It is cross-platform and can be used on multiple operating systems.

  Language:C++385

• cebarobot/flappy-bird-fpga

  Flappy Bird game on FPGA

  Language:Verilog6

• masc-ucsc/esesc

  ESESC: A Fast Multicore Simulator

  Language:C13463

• lizard-52/Xeon-Phi-Notes

  51

• microsoft/calipers

  Criticality-aware Framework for Modeling Computer Performance

  Language:C++277

• thu-cs-lab/verilog-coding-standard

  Recommended coding standard of Verilog and SystemVerilog.

  Language:Verilog332

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.7k380

• MIPT-ILab/mipt-mips

  Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

  Language:C++342141

• MaZirui2001/Zircon

  Language:Scala201

• lizhirui/DreamCoreV2

  Language:C202

• sifferman/labs-with-cva6

  Advanced Architecture Labs with CVA6

  Language:SystemVerilog4925

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.3k699

• arch-simulator-sig/Systemverilog-DIfftest-Env

  Basic systemverilog difftest environment for RTL design

  Language:C51

• WangXuan95/USTC-RVSoC

  An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

  Language:SystemVerilog36075

• os-fpga/Virtual-FPGA-Lab

  This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.

  Language:Tcl14524

• EtienneBarbier/Hyper-V-RHEL-VM

  Guide and scripts for RedHat Enterprise Linux VM on Hyper-V with Enhanced Session Mode

  Language:Shell3211

• openhwgroup/cv32e40x

  4 stage, in-order, compute RISC-V core based on the CV32E40P

  Language:SystemVerilog22552

• openhwgroup/cv32e40x-dv

  CV32E40X Design-Verification environment

  Language:Assembly119

• fredrequin/verilator_xilinx

  Re-coded Xilinx primitives for Verilator use

  Language:Verilog413

• xiazhuo/nscc2022_personal

  NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）

  Language:VHDL533

• ProjectDimlight/SOL-s-Verilog-Cheatsheet-for-Not-So-Beginners

  222

• CnTransGroup/EffectiveModernCppChinese

  《Effective Modern C++》- 完成翻译

  7.9k1.2k

• OpenXiangShan/nexus-am

  Language:C3127

• OSCPU/ysyx

  一生一芯的信息发布和内容网站

  Language:HTML1238

• the-red-pixel/ParallelCraft

  [Draft] ParallelCraft 并行化Minecraft服务端

  Language:Java2