LucaF-dev

LucaF-dev's Stars

• ics-jku/wal

  WAL enables programmable waveform analysis.

  Language:Python13218

• CMU-SAFARI/Sibyl

  Source code for the software implementation of Sibyl proposed in our ISCA 2022 paper: Gagandeep Singh et. al., "Sibyl: Adaptive and Extensible Data Placement in Hybrid Storage Systems using Online Reinforcement Learning" at https://people.inf.ethz.ch/omutlu/pub/Sibyl_RL-based-data-placement-in-hybrid-storage-systems_isca22.pdf

  Language:Python316

• dian-lun-lin/RTLflow

  A GPU acceleration flow for RTL simulation with batch stimulus

  Language:C++907

• abhishekkrthakur/approachingalmost

  Approaching (Almost) Any Machine Learning Problem

  7.3k1.1k

• intel/rohd

  The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

  Language:Dart37367

• TL-X-org/TL-V_Projects

  An overview of TL-Verilog resources and projects

  704

• GuzTech/misato

  RISC-V Processor written in Amaranth HDL

  Language:Python315

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C2.9k562

• olofk/fusesoc

  Package manager and build abstraction tool for FPGA/ASIC development

  Language:Python1.2k244

• kevinconway/remouseable

  Use a reMarkable tablet as a mouse.

  Language:C20712

• supratimdas/NoobsCpu-8bit

  A simple 8bit CPU.

  Language:Verilog251

• The-OpenROAD-Project/OpenLane

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  Language:Python1.3k372

• siliconcompiler/siliconcompiler

  Modular hardware build system

  Language:Python85585

• ChFrenkel/ReckOn

  ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.

  Language:Verilog7517

• google-research/circuit_training

  Language:Python1.1k184

• mortbopet/Ripes

  A graphical processor simulator and assembly editor for the RISC-V ISA

  Language:C++2.6k273

• carlosedp/chiselv

  A RISC-V Core (RV32I) written in Chisel HDL

  Language:Scala9416

• StanfordLegion/legion

  The Legion Parallel Programming System

  Language:C++678145

• olofk/vidbo

  Virtual Development Board

  Language:C576

• wavedrom/wavedrom

  :ocean: Digital timing diagram rendering engine

  Language:JavaScript3k365