MDVasu's Stars
raulbehl/100DaysOfRTL
100 Days of RTL
kevinpinto98/sv-tutorial
SystemVerilog Tutorial
SpinalHDL/VexiiRiscv
Like VexRiscv, but, Harder, Better, Faster, Stronger
rgdagir/ee108
Lab files for EE108 - Digital Systems Design, class taken in Winter/2019
arm-university/VLSI-Fundamentals-Education-Kit
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
leo47007/TPU-Tensor-Processing-Unit
IC implementation of TPU
abejgonzalez/abejgonzalez.github.io
My personal webpage
srimanthtenneti/Systolic_Arrays
This repo contains an implementation of a 2x2 Systolic Array using Verilog HDL. The testbench is also included in the design file.
lirui-shanghaitech/CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
NAvi349/riscv-proc
32-bit 5-Stage Pipelined RISC V RV32I Core
cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
mattvenn/awesome-opensource-asic-resources
lowRISC/opentitan
OpenTitan: Open source silicon root of trust
michaelehab/AES-Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
somyadashora/AMBA-AXI4-Lite
Master and Slave made using AMBA AXI4 Lite protocol.
Developer-Y/cs-video-courses
List of Computer Science courses with video lectures.
Anirudh-Iruvanti/RISC-V-Processor
5 Staged Pipelined RISC V Processor
hanysalah/Design-Pattern-in-SV
This repo is created to include illustrative examples on object oriented design pattern in SV