/RISC-V-Single-Cycle-CPU

A RISC-V 32bit single-cycle CPU written in Logisim

Primary LanguageVerilogMIT LicenseMIT

RISC-V Single Cycle CPU

Cover Image

Result Image

Notes

  • Single page version can achieve ~300 Hz clock rate on a i7-6700K computer.

Terms and Conditions

The software Logisim-evoluion is released under the terms of the GNU GENERAL PUBLIC LICENSE (GPL). For your convenience, the jar file is included in this repository in accordance with the redistribution guideline of the GPL-3.0 license agreement.

This project is under MIT License.