/64-bit-Single-Cycle-RISC-V-Core

Digital Design and ASIC Implementation of a 64-bit Single Cycle RISC-V Core that supports RV32I ISA

Primary LanguageSystemVerilogMIT LicenseMIT

64-bit-Single-Cycle-RISC-V-Core

Digital Design and ASIC Implementation of a 64-bit Single Cycle RISC-V Core that supports RV32I ISA