MahmouodMagdi
Digital IC Design and Verification Engineer with an extreme interest in Digital IC Front-End Design, Verification, and ASIC Implementation
Cairo, Egypt
Pinned Repositories
256-bit-Modular-Adder-Subtractor
Hardware Implementation of a Modular Adder/Subtractor
64-bit-Single-Cycle-RISC-V-Core
Digital Design and ASIC Implementation of a 64-bit Single Cycle RISC-V Core that supports RV32I ISA
ASIC-Physical-Design-Roadmap
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
Asynchronous-FIFO
A verilog implementation of an aynchronous FIFO (First In First Out).
Clock-Domain-Crossing-Synchronizers
Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossing solutions in digital systems.
Design-and-Verification-of-a-PCIe-Packet-Detector
Digital Design of a PICe packet detector FSM that detects whether the packet is a good or pad.
Memory-System-Verilog-Class-based-Testing-Environment
A SystemVerilog Class-Based Testing Environment to test 32*32 Memory Design
RTL-Design-of-ARM-based-AHB-to-APB-Bridge
Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way
RTL-to-GDS-Implementaton-of-Low-Power-Configurable-Multi-Clock-Digital-System-
It is resposable of receiving commands through UART receiver to do different system functions as register file reading/writing or doing some processing using ALU block and send result as well as CRC bits of result using 4 bytes frame through UART transmitter communication protocol.
RTL_Codes
This Repo. cotains different Verilog Codes of different Logic Units
MahmouodMagdi's Repositories
MahmouodMagdi/Clock-Domain-Crossing-Synchronizers
Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossing solutions in digital systems.
MahmouodMagdi/256-bit-Modular-Adder-Subtractor
Hardware Implementation of a Modular Adder/Subtractor
MahmouodMagdi/Asynchronous-FIFO
A verilog implementation of an aynchronous FIFO (First In First Out).
MahmouodMagdi/ASIC-Physical-Design-Roadmap
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
MahmouodMagdi/Design-and-Verification-of-a-PCIe-Packet-Detector
Digital Design of a PICe packet detector FSM that detects whether the packet is a good or pad.
MahmouodMagdi/RTL_Codes
This Repo. cotains different Verilog Codes of different Logic Units
MahmouodMagdi/64-bit-Single-Cycle-RISC-V-Core
Digital Design and ASIC Implementation of a 64-bit Single Cycle RISC-V Core that supports RV32I ISA
MahmouodMagdi/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
MahmouodMagdi/cvfpu
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
MahmouodMagdi/ghdl
VHDL 2008/93/87 simulator
MahmouodMagdi/Memory-System-Verilog-Class-based-Testing-Environment
A SystemVerilog Class-Based Testing Environment to test 32*32 Memory Design
MahmouodMagdi/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
MahmouodMagdi/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
MahmouodMagdi/RTL-Design-of-ARM-based-AHB-to-APB-Bridge
Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way
MahmouodMagdi/RTL-to-GDS-Implementaton-of-Low-Power-Configurable-Multi-Clock-Digital-System-
It is resposable of receiving commands through UART receiver to do different system functions as register file reading/writing or doing some processing using ALU block and send result as well as CRC bits of result using 4 bytes frame through UART transmitter communication protocol.
MahmouodMagdi/UART-Communication-Protocol-using-Spartan-6-Xilinx-FPGA
MahmouodMagdi/Awesome-Profile-README-templates
A collection of awesome readme templates to display on your profile
MahmouodMagdi/Fixed-Point-Multiplications
Several methods are presented in this repository to multiply signed and unsigned operands, including the sequential add-shift method, the Booth algorithm, and an array multiplier.
MahmouodMagdi/MahmouodMagdi
MahmouodMagdi/Modular-Inverse
A SystemVerilog Implementation of the Montgomery Modular Inverse with Binary Extended Euclidean Algorithm
MahmouodMagdi/Modular-Multiplier
A System Verilog Design of the Shift-sub Modular Multiplier Algorithm
MahmouodMagdi/PDK_ONC5
Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library
MahmouodMagdi/riscv-isa-manual
RISC-V Instruction Set Manual
MahmouodMagdi/riscv-tools
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
MahmouodMagdi/TaskScheduler
a hardware task scheduler design
MahmouodMagdi/u-boot-xlnx
The official Xilinx u-boot repository
MahmouodMagdi/UART-Communication-Protocol
Verilog Hierarical Design of the UART