Pinned Repositories
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cv32e20-dv
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
cve2
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original Zero-RI5CY work from ETH Zurich and Ibex work from lowRISC.
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cv32e20-dv
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
cve2
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
MarioOpenHWGroup's Repositories
MarioOpenHWGroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
MarioOpenHWGroup/cv32e20-dv
MarioOpenHWGroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
MarioOpenHWGroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
MarioOpenHWGroup/cve2
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original Zero-RI5CY work from ETH Zurich and Ibex work from lowRISC.