Pinned Repositories
cv32e41p
4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
riscv-cfi
This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.
programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
riscv-cfi
This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual
MarkHillHuawei's Repositories
MarkHillHuawei/cv32e41p
4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
MarkHillHuawei/programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
MarkHillHuawei/riscv-cfi
This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.