Pinned Repositories
ao486
The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.
ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
black-parrot-branch-predictor
Branch Predictor Optimization for BlackParrot
Caravel_FPU
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Chisel-Training
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Cores-SweRV
SweRV EH1 core
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
MasterJerryZh's Repositories
MasterJerryZh/ao486
The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.
MasterJerryZh/ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
MasterJerryZh/black-parrot-branch-predictor
Branch Predictor Optimization for BlackParrot
MasterJerryZh/Caravel_FPU
MasterJerryZh/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
MasterJerryZh/Chisel-Training
MasterJerryZh/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
MasterJerryZh/Cores-SweRV
SweRV EH1 core
MasterJerryZh/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
MasterJerryZh/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
MasterJerryZh/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
MasterJerryZh/imperas-riscv-tests
MasterJerryZh/LM-RISCV-DV
An Open-Source Design and Verification Environment for RISC-V
MasterJerryZh/openc910
OpenXuantie - OpenC910 Core
MasterJerryZh/Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
MasterJerryZh/ridecore
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
MasterJerryZh/riscv-arch-test
MasterJerryZh/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
MasterJerryZh/riscv-dv
Random instruction generator for RISC-V processor verification
MasterJerryZh/riscv-soc-book
关于RISC-V你所需要知道的一切
MasterJerryZh/rocket-chip
Rocket Chip Generator
MasterJerryZh/verilog_test
just for test!
MasterJerryZh/vroom
VRoom! RISC-V CPU
MasterJerryZh/XiangShan
Open-source high-performance RISC-V processor
MasterJerryZh/XS-Verilog-Library