MasterPlayer

adxl345-sv

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device

Analog-Device-AXI-Reconfiguration

FPGA Based reconfiguration interface from AXI to SPI Analog Device, holds readed data and sends data from AXI to AD over SPI/SDIO interface

axis_iic_bridge

FPGA implementation I2C bridge with support AXI-Stream protocol

axis_uart_bridge

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

fpga-loader-SelectMap

FPGA bitstream loader for xilinx using SelectMAP

lcd-st7789-sv

simple demo hardware code for implement access to ST7789 LCD display from FPGA

rmii-ethernet-mac

RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and without MDIO interface support

xilinx-sdk

projects, sources, files for working in xilinx sdk.

xilinx-sv

SystemVerilog component lib

xilinx-vhdl

MasterPlayer/rmii-ethernet-mac

RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and without MDIO interface support

MasterPlayer/lcd-st7789-sv

simple demo hardware code for implement access to ST7789 LCD display from FPGA

MasterPlayer/axis_iic_bridge

FPGA implementation I2C bridge with support AXI-Stream protocol

MasterPlayer/xilinx-vhdl

MasterPlayer/adxl345-sv

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device

MasterPlayer/fpga-loader-SelectMap

FPGA bitstream loader for xilinx using SelectMAP

MasterPlayer/Analog-Device-AXI-Reconfiguration

FPGA Based reconfiguration interface from AXI to SPI Analog Device, holds readed data and sends data from AXI to AD over SPI/SDIO interface

MasterPlayer/axi-memory-manager

Full-Duplex support memory manager for transmit data from S_AXIS and sending data to M_AXI_FULL, or receive data over M_AXI_FULL and sending data to M_AXIS

MasterPlayer/axi_memory_writer_intr

Component for writing to DDR memory over AXI interface from AXI-Stream to AXI full with support interrupts

MasterPlayer/axis-data-collector

AXI-Stream data collector grouped by ID, USER. Component Accumulates input data streams, and establish this data, when quantity of them exceeds limit

MasterPlayer/axis_register

axi-stream output register for alternative output fifo

MasterPlayer/micron-nor-ctrlr

Micron Flash interface with support x4 data width and supports AXI-Stream interface

MasterPlayer/arp-table-tdp

ARP Table based upon true dual port ram with support setting number of elements

MasterPlayer/axi-lite-register-file

AXI Lite register file for registers with configurable count of registers

MasterPlayer/axi-timer-averager

AXI controlled timer for measurement average time of performance

MasterPlayer/xilinx-sv

SystemVerilog component lib

MasterPlayer/axi_dump_gen

AXI-Stream data generator with support AXI-Lite configuration

MasterPlayer/axi_memory_reader_pkt

Компонент для выполнения команд чтения из памяти и отправки значений на шину AXI-Stream. Система прерываний не поддерживается

MasterPlayer/axi_memory_writer_pkt_intr

Component for writing data from axi-stream to axi-full with support interrupt signal for each packet. packet size cannot greater MAX_BURST words count. Simple component

MasterPlayer/axis-data-checker

axi-stream data checker for indication about errors and statistics counters

MasterPlayer/axis-threshold-ctrl

threshold controller for limit data speed on AXI-Stream bus with sync/async support

MasterPlayer/axis-udp-pkg

simple udp packager for incapsulate input stream to udp datagrams

MasterPlayer/axis-udp-pkg-prm

parametrized UDP packet former with support various widths and header size

MasterPlayer/axis-udp-pkg-vs

Component for incapsulate input data to UDP datagrams with Eth/IP/udp headers with various size support

MasterPlayer/axis_adxl345_vhd

Library for processing and configuration adxl345 from FPGA with control from processor

MasterPlayer/i2s-receiver

i2s receiver data from digital microphone writed on SystemVerilog

MasterPlayer/mp_irq_generator

IRQ generator with configurable duration

MasterPlayer/mp_irq_retryer

interrupt retry engine for regenerate interrupts signal

MasterPlayer/sys-mng-drp-ctrlr

System Monitor/Manager DRP controller for reading data from IP core over DRP protocol

MasterPlayer/zturn

sources, modules, components for zturn development board