MortezaRezaalipour

AxMAP

AxMAP: Making Approximate Adders Aware of Input Patterns

A-Simple-OpenCL-Project

A simple OpenCL project for parallel processing

AxMAP

AxMAP: Making Approximate Adders Aware of Input Patterns

ErrorEval

This is the open source code for our paper titled "ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing"

helpful_vhdl_open_source

Simple VHDL examples using ghdl as compiler and wave generating

JPEG_Encoder_VHDL

A Simple JPEG Encoder in VHDL

MortezaRezaalipour

Synthesizable-VHDL-Implementation-of-Cyclic-Codes

My BSc Project: Implementation & Evaluation of a cyclic code using FPGA

VerilogChecker

A circuit equivalence checker given an error threshold for Approximate Computing

VerilogPADAnalyzer

VerilogPADAnalyzer is a Python application designed to analyze and report the Power, Area, and Delay (PAD) of Verilog input circuits.

MortezaRezaalipour/ErrorEval

This is the open source code for our paper titled "ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing"

MortezaRezaalipour/VerilogPADAnalyzer

VerilogPADAnalyzer is a Python application designed to analyze and report the Power, Area, and Delay (PAD) of Verilog input circuits.

MortezaRezaalipour/JPEG_Encoder_VHDL

A Simple JPEG Encoder in VHDL

MortezaRezaalipour/Synthesizable-VHDL-Implementation-of-Cyclic-Codes

My BSc Project: Implementation & Evaluation of a cyclic code using FPGA

MortezaRezaalipour/VerilogChecker

A circuit equivalence checker given an error threshold for Approximate Computing

MortezaRezaalipour/A-Simple-OpenCL-Project

A simple OpenCL project for parallel processing

MortezaRezaalipour/AxMAP

AxMAP: Making Approximate Adders Aware of Input Patterns

MortezaRezaalipour/helpful_vhdl_open_source

Simple VHDL examples using ghdl as compiler and wave generating

MortezaRezaalipour/MortezaRezaalipour

MortezaRezaalipour/z3log