MortezaRezaalipour
I am pursuing my Ph.D. at Università della Svizzera Italiana (USI).
Lugano, Ticino, Switzerland
MortezaRezaalipour's Stars
Z3Prover/z3
The Z3 Theorem Prover
msys2/msys2.github.io
The MSYS2 homepage
berkeley-abc/abc
ABC: System for Sequential Logic Synthesis and Formal Verification
The-OpenROAD-Project/OpenSTA
OpenSTA engine
ultraembedded/riscv_soc
Basic RISC-V Test SoC
eth-sri/fastsmt
Learning to Solve SMT Formulas Fast
acarcher/risc
16-bit CPU written in VHDL
SJTU-ECTL/ALSRAC
ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
scale-lab/ABACUS
ABACUS is a tool for approximate logic synthesis
JulyWitch/vhdl_ghdl_examples
Simple VHDL examples using ghdl as compiler and wave generating
changmg/VACSEM
VACSEM: Verifying Average Errors in Approximate Circuits Using Simulation-Enhanced Model Counting
SalvatoreBarone/pyALS
Python implementation of the catalog-based Aig-rewriting approximate Logic Synthesis technique
changmg/ResubALS
Efficient resubstitution-based approximate logic synthesis
changmg/ALS-preliminaries
cosmcif/cookbook
Just recipes I wanna keep track of
marcocosta97/SOP-ApproximateLogicSynthesis
Approximate Logic Synthesis and Bi-Decomposition of Sum Of Products forms
mohrez86/alpharepair_d4j
The source code from the original AlphaRepair (automated program repair tool) replication package, along with added documentation for ease of use.
sat-group/pysat
A toolkit for SAT-based prototyping in Python
zohdit/DeepHyperion-Kickoff
zohdit/tagger
AliJavadiGithub/Asynchronous-Advantage-Actor-Critic
amahzoon/Verilog-Benchmarks
This repository includes set of Verilog benchmarks
changmg/ALSRAC
ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
cosmcif/raytracer
USI Computer Graphics Rendering Competition 2023
mohrez86/fauxpy
An automated fault localization tool for Python programs.
zohdit/DeepAtash
zohdit/DeepHyperion
zohdit/DeepHyperion-MNIST
zohdit/feature-map
zohdit/unboxer
Heatmap Clustering to Understand the Misbehaviours Exposed by Automatically Generated Test Inputs