MrCappuccino

MrCappuccino's Stars

• 521xueweihan/GitHub520

  :kissing_heart: 让你“爱”上 GitHub，解决访问时图裂、加载慢的问题。（无需安装）

  Language:Python24.1k2.3k

• The-OpenROAD-Project/asap7_pdk_r1p7

  Language:Perl133

• yian521/OpenC910_Modified

  commit rtl and build cosim env

  Language:Verilog13

• KasuganoSoraaa/simple-AXI2AHB-bridge

  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc

  Language:Verilog3311

• wudayemen/gen_apb_file

  Language:Python6327

• brown9804/PCIe_physical_layer

  Implementation of the PCIe physical layer

  Language:Verilog3110

• WangXuan95/UniPlug-FPGA

  一个FPGA核心板设计，体积小、低成本、易用、扩展性强。

  Language:Verilog7914

• WangXuan95/FPGA-MPEG2-encoder

  An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。

  Language:Verilog11623

• WangXuan95/FPGA-Gzip-compressor

  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据，输出标准的GZIP格式，即常见的 .gz / .tar.gz 文件的格式。

  Language:Verilog10223

• WangXuan95/FPGA-FOC

  An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

  Language:Verilog587181

• WangXuan95/FPGA-JPEG-LS-encoder

  An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

  Language:Verilog22244

• cxdzyq1110/posture_recognition_CNN

  To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very difficult as well, because usually it is very slow and power-consuming, and requires a very large memory space. Here we focus on real-time posture recognition, and try to make the machine "know" what posture we make. The posture recognition system is consisted of DE10-Nano SoC FPGA Kit, a camera, and an HDMI monitor. SoC FPGA captures video streams from the camera, recognizes human postures with a CNN model, and finally shows the original video and classification result (standing, walking, waving, etc.) via HDMI interface.

  Language:Verilog5117

• m-labs/tdc-core

  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs

  Language:Verilog5928

• defparam/PCI2Nano-RTL

  An open source FPGA PCI core & 8250-Compatible PCI UART core

  Language:Verilog405

• Summer-Summer/ComputerArchitectureLab

  This repository is used to release the Labs of Computer Architecture Course from USTC

  Language:Verilog3614

• fpgasystems/groundhog

  Groundhog - Serial ATA Host Bus Adapter

  Language:Verilog219

• yuxguo/USTC-ComputerArchitecture-2020S

  Code for "Computer Architecture" in 2020 Spring.

  Language:Verilog298

• bluespec/Accel_AES

  Language:Verilog157

• tomverbeure/intel_jtag_primitive_blog

  How to use the Intel JTAG primitive without using virtual JTAG

  Language:Verilog165

• ztgao/ConvNN_FPGA_Accelerator

  Language:Verilog135

• Hsury/AES-Cipher-Chip

  An AES cipher chip supporting 128/256 ECB mode with 8-bit half-duplex data bus, being taped out using SMIC 130nm process.

  Language:Verilog72

• tomtor/HDL-deflate

  FPGA implementation of deflate (de)compress RFC 1950/1951

  Language:Verilog596

• THU-DSP-LAB/ventus-gpgpu

  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

  Language:Scala65877

• FPGA-Networking/HyperParser

  Language:Verilog2910

• sangwoojun/bluedbm

  BlueDBM hw/sw implementation using the bluespecpcie PCIe library

  Language:Verilog108

• sergeykhbr/riscv_vhdl

  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

  Language:Verilog634104

• lgziyan/Modelsim_Tcl_Simulation

  ModelSim的TCL脚本仿真流程

  Language:Verilog5

• someone755/ddr3-controller

  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

  Language:Verilog6310

• funannoka/SoC-Design-DDR3-Controller

  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog

  Language:Verilog3016

• P3Stor/P3Stor

  A PCIe interface flash storage system

  Language:Verilog65