Quartus 21 prime lite cannot synthesis request and usage of module member

[Naminar]

tlb-v/tlb.v

Lines 121 to 128 in 40ba9d6

	if(ways[0].w.tag[set] == tag && ways[0].w.pcid[set] == pcid) begin
	// plru[set][0] = 1'b0;
	// plru[set][1] = 1'b0;
	// plru[set][3] = 1'b0;
	plru[set] = new_plru(plru[set], 7'b0001011, 7'b0000000);
	ta[SADDR-1:SPAGE] <= ways[0].w.pa[set];
	end else if(ways[1].w.tag[set] == tag && ways[1].w.pcid[set] == pcid) begin
	// plru[set][0] = 1'b0;

Caution

Xilinx able to do this.

[Naminar]

Same question here.