/Single-cycle-RISC-V-processor

Primary LanguageVerilog

Single-cycle-RISCV-processor

Verilog code for a 32-bit pipelined Single Cycle RISC-V processor (RV32I) processor.

The project is implemented using Vivado software

RTL Schematic of processor image

RISCV processor with Controlpath and Datapath Modules image

Testbench results image

Reference material:

Computer Organization and Design: The Hardware/Software Interface RISC-V edition Authors - DAVID A PATTERSON , JOHN L HENNESSY