NiharGowdaS

Interested in VLSI design, FPGA and ASIC

Pinned Repositories

MP_EE_24-V
Language:Verilog20
ASIC-Design-Flow-using-Openlane
00
Image-processing-using-Verilog
Language:Verilog00
lz4_compression_caravel
Language:Verilog00
Music-Synthesizer---Karplus-Strong-Algorithm
Language:Verilog00
RISC-V-pipeline-processor
Language:Verilog00
rvcorep_caravel
Language:Verilog00
Single-cycle-RISC-V-processor
Language:Verilog00

NiharGowdaS's Repositories

NiharGowdaS/rvcorep_caravel
Language:Verilog
NiharGowdaS/Image-processing-using-Verilog
Language:Verilog
NiharGowdaS/lz4_compression_caravel
Language:Verilog
NiharGowdaS/MP_EE_24-V
Language:Verilog2
NiharGowdaS/Music-Synthesizer---Karplus-Strong-Algorithm
Language:Verilog
NiharGowdaS/ASIC-Design-Flow-using-Openlane
NiharGowdaS/RISC-V-pipeline-processor
Language:Verilog
NiharGowdaS/Single-cycle-RISC-V-processor
Language:Verilog