NikhilRout

NikhilRout's Stars

• adam-maj/tiny-gpu

  A minimal GPU design in Verilog to learn how GPUs work from the ground up

  Language:SystemVerilog7.1k6824531

• chipsalliance/chisel

  Chisel: A Modern Hardware Design Language

  Language:Scala4k1501.1k595

• shaily99/advice

  A repository of links with advice related to grad school applications, research, phd etc

  2.1k351193

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.6k601379

• vortexgpgpu/vortex

  Language:Verilog1.2k38118260

• aolofsson/oh

  Verilog library for ASIC and FPGA designers

  Language:Verilog1.2k10035286

• ucb-bar/gemmini

  Berkeley's Spatial Array Generator

  Language:Scala80630184168

• schoeberl/chisel-book

  Digital Design with Chisel

  Language:TeX7653618142

• alexforencich/verilog-axis

  Verilog AXI stream components for FPGA implementation

  Language:Python7364724225

• xiaop1/Verilog-Practice

  HDLBits website practices & solutions

  Language:Verilog686116178

• karanwxliaa/Research-for-UG-Students

  Research programs for Undergraduate students

  58411063

• trivialmips/nontrivial-mips

  NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

  Language:SystemVerilog57527197

• Infatoshi/cuda-course

  Language:Cuda48112172

• secworks/aes

  Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

  Language:Verilog334279124

• schoeberl/chisel-examples

  Chisel examples and code snippets

  Language:Tcl23020978

• WangXuan95/FPGA-CAN

  An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

  Language:Verilog2188467

• nandland/spi-slave

  SPI Slave for FPGA in Verilog and VHDL

  Language:Verilog18012668

• abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU

  IC implementation of Systolic Array for TPU

  Language:Verilog1472124

• vortexgpgpu/vortex_tutorials

  1356644

• gnodipac886/ViT-FPGA-TPU

  FPGA based Vision Transformer accelerator (Harvard CS205)

  Language:SystemVerilog83228

• AngeloJacobo/RISC-V

  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

  Language:Verilog65715

• Andrei0105/MIPS-multi-cycle

  MIPS multi cycle Verilog implementation based on Computer Organization and Design by David A. Patterson and John L. Hennessy

  Language:Verilog20105

• Tinycl/ISCApapers

  International Symposium on Computer Architecture papers 收集历年计算机体系结构顶级会议ISCA的论文

  Language:Python11203

• matbi86/01_ai_accelerator_basic_for_student

  ai_accelerator_basic_for_student (no solve)

  Language:Verilog10201

• Th-Havy/SimpleDPCM

  This repository contains an example of Differential Pulse-Code Modulation (DPCM) written in MATLAB.

  Language:MATLAB8112

• rithan2001/Database-to-shortlist-Universities_VLSI-only-

  How to shortlist universities for MS in US?

  41

• robotman2412/nebula-risc-v

  A collaborative RISC-V CPU project

  Language:Scala4260

• zyongye/LC-3

  Verilog Realization of Little Computer 3, a processor used for book "Intro to Computing Systems"

  Language:Verilog40

• FloofyJin/chisel-ai-accelerator

  Language:Scala2100

• rithan2001/Undergraduate-Internship-details

  1