Pinned Repositories
CMPN405-Computer-Networks-Project
CMPS201_2023
This repo has all the material we need for the CMPS201 Microprocessors course. I will add to it each lab.
Control-Project-ELCN304
Daily-Quran
DCSK
Digital Design and FPGA Implementation of Differential Chaos Shift-Keying Modem
Hany-s-Revenge
A microprocessors educational game. the player is trapped in an office, they have to defuse the bomb by answering some X86 Assembly and 8086 related questions.
Schem2GDS_SAR_ADC
SAR ADC Digital Control Logic -> 100 MSps and 1.1 GHz system frequency. For CND211
UVM_OC8051_ALU
A UVM verification environment for the OpenCores implementation of the Intel 8051 ALU.
VP_Harvard_MIPS
A 32-bit microprocessor with 42 instructions (including multiplication and division) and 8 X 32 registers and 2048 X 32 Ram with shared stack. An assembler is also available to write programs on the microprocessor using 8086-like assembly.
wildwest
CMPN201 Microprocessors assembly multiplayer game using serial communication.
OmarAmer01's Repositories
OmarAmer01/CMPS201_2023
This repo has all the material we need for the CMPS201 Microprocessors course. I will add to it each lab.
OmarAmer01/VP_Harvard_MIPS
A 32-bit microprocessor with 42 instructions (including multiplication and division) and 8 X 32 registers and 2048 X 32 Ram with shared stack. An assembler is also available to write programs on the microprocessor using 8086-like assembly.
OmarAmer01/UVM_OC8051_ALU
A UVM verification environment for the OpenCores implementation of the Intel 8051 ALU.
OmarAmer01/CMPN405-Computer-Networks-Project
OmarAmer01/Control-Project-ELCN304
OmarAmer01/Daily-Quran
OmarAmer01/DCSK
Digital Design and FPGA Implementation of Differential Chaos Shift-Keying Modem
OmarAmer01/Hany-s-Revenge
A microprocessors educational game. the player is trapped in an office, they have to defuse the bomb by answering some X86 Assembly and 8086 related questions.
OmarAmer01/ipyxact
Python-based IP-XACT parser
OmarAmer01/Matching-Network-Designer
This program designs the matching network parameters for a given load and transmission line.
OmarAmer01/Numerical-Analysis
Mathematical tasks and problems solved with python.
OmarAmer01/OmarAmer01
OmarAmer01/PopQuiz-
A Python Trivia Game.
OmarAmer01/Schem2GDS_SAR_ADC
SAR ADC Digital Control Logic -> 100 MSps and 1.1 GHz system frequency. For CND211
OmarAmer01/wildwest
CMPN201 Microprocessors assembly multiplayer game using serial communication.
OmarAmer01/Project-2-ELCN446
Project 2 ELCN446
OmarAmer01/vonNeumann-RISC-Processor-CMPN301
The processor in this project has a RISC-like instruction set architecture. There are eight 4-byte general purpose registers; R0, till R7. Another two general purpose registers, One works as a program counter (PC). And the other, works as a stack pointer (SP); and hence; points to the top of the stack. The initial value of SP is (2^32-2). The memory address space is 1 MB of 16-bit width and is word addressable. ( N.B. word = 2 bytes) When an interrupt occurs, the processor finishes the currently fetched instructions (instructions that have already entered the pipeline), then the address of the next instruction (in PC) is saved on top of the stack, and PC is loaded from address 1 of the memory. To return from an interrupt, an RTI instruction loads the PC from the top of stack, and the flow of the program resumes from the instruction after the interrupted instruction.