OmarAmer01

OmarAmer01's Stars

• twitter/the-algorithm

  Source code for Twitter's Recommendation Algorithm

  Language:Scala62.3k33995012.2k

• aolofsson/awesome-opensource-hardware

  List of awesome open source hardware tools, generators, and reusable designs

  Language:Python1.9k6915172

• grumpycoders/pcsx-redux

  The PCSX-Redux project is a collection of tools, research, hardware design, and libraries aiming at development and reverse engineering on the PlayStation 1. The core product itself, PCSX-Redux, is yet another fork of the Playstation emulator, PCSX.

  Language:C++65223219104

• stnolting/neoTRNG

  🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

  Language:VHDL1716119

• digital-design-hq/Digital-Resources

  53305

• rkharris12/fpga_bitcoin_miner

  Language:VHDL5071028

• ogamespec/psxrev

  Sony PlayStation PCB/chips reverse engineering.

  Language:C#25202

• SoCFPGA-learning/Chameleon96

  The Chameleon96™ board, based on Intel® Cyclone V SoC FPGA

  Language:HTML13602

• A-bahaa/Sharify-Documentation

  Sharify is a serverless web app that allows you to share, preview and save your last month on Spotify seamlessly.

  Language:JavaScript12100

• Mostafa-Hassanien/-A-32-bit-5-stage-Pipelined-MIPS-based-RISC-Core-based-on-Harvard-Architecture-

  This project aims to implement a 32-bit 5-stage pipelined High-performance MIPS-based RISC Core based on Harvard Architecture. The MIPS processor was designed using MIPS ISA (Instruction Set Architecture) and divided into three main modules: datapath unit, control unit, and hazard unit. The processor is tested to run two programs: GCD Calculation of two numbers and Factorial Calculation of a number. Programs are written in MIPS assembly code, then converted to machine code. Verilog HDL language is used on ModelSim Simulation tool to verify the functional simulation of the processor and compare between five-stage pipelined MIPS processor and single-cycle MIPS processor regarding performance analysis. Keywords: Pipelined MIPS Processor, Harvard Architecture, MIPS Assembly, Functional Simulation, Datapath, Hazard Unit.

  Language:Verilog7104

• junqiuzhang/DCSK

  DCSK

  Language:MATLAB6101

• mohamedemad2251/SMART-HOME-SYSTEM

  A repository for the final graduation project in the AMIT Diploma 2023 (Embedded Systems)

  Language:C24

• 2Martina/RiscV-SingleCycle

  Language:Verilog10

• Hossam-Amer/Signal-viewer

  web application using html ,CSS ,java script ,plotly library .That provides showing two signals and controlling the way it's plotted ,linking the two signals and downloading any needed interval statistics (std ,min ,max ,avg..) and it's graph as a pdf file

  Language:JavaScript10

• IamDestruction/I2C_Master_Verilog

  Designing and implementation of I2C master in verilog.

  Language:Verilog1

• vdalex/dcsk

  DCSK PLC

  1

• Yahia-EL-Alfy/vminds-pg-backend

  Language:HTML11

• yayaelbasha/Single-Cycle-RISC-V-32I-Processor

  Language:Verilog10