OpenResearchInstitute/dvb_fpga

Issues

• Simulation

  #21 opened a month ago by HagarYassin
  0

• Consulting for choosing proper hardware

  #17 opened a year ago by sumanthraikar
  0

• Data rate supported on ZYNQ 7010

  #20 opened a year ago by iottrends
  0

• Running locally issue

  #18 opened a year ago by noriaka
  4

• AXI interface issue

  #16 opened a year ago by davidfhorowitz
  1

• Unable to build zc706 design from tcl script

  #15 opened a year ago by davidfhorowitz
  14

• vhdl compile errors

  #14 opened a year ago by indieorganic
  2

• IP Integrator?

  #11 opened 3 years ago by Abraxas3d
  0

• correct modcods and frame types

  #12 opened 2 years ago by Abraxas3d
  0

• AXI bit interleaver reads invalid AXI tdata

  #7 opened 4 years ago by suoto
  0

• Add support for byte qualifier to axi_file_reader

  #1 opened 4 years ago by suoto
  1

• Add Yosys CI run

  #4 opened 4 years ago by suoto
  0

• Bit interleaver does not synthesize with Vivado

  #5 opened 4 years ago by suoto
  0

• Support open source simulators

  #2 opened 4 years ago by suoto
  1

• Translate third_party/wb2axip/rtl/skidbuffer.v to VHDL

  #3 opened 4 years ago by suoto
  0