PandABlocks/PandABlocks-FPGA
VHDL functional blocks with their simulations and test sequences
VHDLApache-2.0
Issues
- 1
Investigate PCOMP Table module
#219 opened - 0
Tidy Encoders.vhd
#217 opened - 2
- 0
- 0
Implement DDMI for SFPs
#212 opened - 0
Fix upload/download artifacts
#210 opened - 0
- 4
How to get the input with the FMC_ACQ430
#203 opened - 3
Put/Post is forbiddon from ...
#202 opened - 0
Write PID Controller block
#201 opened - 5
changing/giving MAC-addresse
#200 opened - 0
Investigate FMC ACQ427 Jitter
#199 opened - 0
Test current enDat encoder capabilities
#198 opened - 0
- 0
- 0
PandABrick encoders
#184 opened - 4
- 9
- 3
- 0
Send timestamp over SFP via PandA sync
#175 opened - 0
Parameter default values in .block.ini files
#173 opened - 1
Add support for hardware derived timestamp
#172 opened - 2
- 4
- 0
Adding
#169 opened - 40
ADD Block POSENC
#168 opened - 2
- 2
Support for ML model deployment
#166 opened - 0
The us_system block should be defined as a "pure" extension block without any VHDL implementation
#165 opened - 2
- 0
EVR: Implement event forwarding on EVR TX
#159 opened - 0
EVR: Vary MGT refclk frquency
#158 opened - 0
Add version number to created devicetree
#154 opened - 2
- 0
Latch link down errors on SFP
#151 opened - 0
Populate clock_target and clock_actual
#150 opened - 0
- 0
PandABrick: DCARD mode
#148 opened - 1
PandABrick: tidy up sfp_pand_sync
#147 opened - 1
PandABrick: convert verilog file to VHDL
#146 opened - 0
PandABrick: LEDs and I2C
#145 opened - 0
PandABrick: tidy up encoders module
#144 opened - 1
- 1
- 0
Investigate Dynamic Function Exchange
#135 opened - 0
Consider the use of HOG
#134 opened - 0
Remove unused/bogus resets
#133 opened - 6
Wrong initial value from PCAP capture
#129 opened - 0
- 4
Support the CAENels FMC-Pico-1M4
#125 opened