QifanWang28's Stars
krahets/hello-algo
《Hello 算法》：动画图解、一键运行的数据结构与算法教程。支持 Python, Java, C++, C, C#, JS, Go, Swift, Rust, Ruby, Kotlin, TS, Dart 代码。简体版和繁体版同步更新，English version ongoing
Anduin2017/HowToCook
程序员在家做饭方法指南。Programmer's guide about how to cook at home (Simplified Chinese only).
TheAlgorithms/C-Plus-Plus
Collection of various algorithms in mathematics, machine learning, computer science and physics implemented in C++ for educational purposes.
jobbole/awesome-python-cn
Python资源大全中文版，包括：Web框架、网络爬虫、模板引擎、数据库、数据可视化、图片处理等，由「开源前哨」和「Python开发者」微信公号团队维护更新。
kenjihiranabe/The-Art-of-Linear-Algebra
Graphic notes on Gilbert Strang's "Linear Algebra for Everyone"
CopyTranslator/CopyTranslator
Foreign language reading and translation assistant based on copy and translate.
liguodongiot/llm-action
本项目旨在分享大模型相关技术原理以及实战经验（大模型工程化、大模型应用落地）
pot-app/pot-desktop
🌈一个跨平台的划词翻译和OCR软件 | A cross-platform software for text translation and recognition.
rd2coding/Road2Coding
编程之路
chipsalliance/rocket-chip
Rocket Chip Generator
ShiqiYu/CPP
Lecture notes, projects and other materials for Course 'CS205 C/C++ Program Design' at Southern University of Science and Technology.
maxim5/cs229-2018-autumn
All notes and materials for the CS229: Machine Learning course by Stanford University
harvard-edge/cs249r_book
Collaborative book Machine Learning Systems
circuitnet/CircuitNet
CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)
linyuxuanlin/Wiki_MkDocs
基于 MkDocs & Material theme 的个人知识库
bmurmann/ADC-survey
ADC Performance Survey 1997-2024 (ISSCC & VLSI Circuit Symposium)
doonny/basic_knowledge
Things to learn for new students in the Lab for AI chips and systems of BJTU .
limbo018/Limbo
Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
haiguanl/DQN_GlobalRouting
Applying Deep Q-learning for Global Routing
luckyrantanplan/nthu-route
VLSI EDA Global Router
user-xleo/DNN-Accelerator
A DNN Accelerator implemented with RTL.
UTDA-group/BoxRouter
BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2D global routing and layer assignment. The 2D global routing is equipped with several ideas: such as robust negotiation-based A* search for routing stability, and topology-aware wire ripup for flexibility and so on. After 2D global routing, 2D-to-3D mapping is done by the layer assignment which is powered by progressive via/blockage-aware integerlinear programming.
Kareem-Emad/DCNN-Accelerator
Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.
pietro-caragiulo/survey-DAC
ys-2020/6.5930_final_project
Final project for MIT 6.5930 Course
eecheng87/MNIST_accelerator
Accelerating CNN in hardware aspect
ryroy912/SHIFT_CNN_hw_accelerator
Design and implementation of a customized FPGA/ASIC circuit to accelerate this operation could help us reduce computational-cost, latency, and power consumption at an acceptable trade-off of a minute reduction in accuracy. (4x reduction in power consumption, 2x reduction in no. of MAC operations, accuracy reduction of just 1%)
Shaanrs7/CNNDigitRec
Digit Recognition using Convolutional Neural Networks, Accelerated on a Zedboard
aabotaleb/SNAPE-FP
SNAPE-FP: SqueezeNet CNN with Accelerated Pooling Layers Extension based on IEEE-754 Floating Point Implementation through SW/HW Partitioning On ZYNQ SoC
vishalgoyall/1-D_CNN_HW_generator
The goal of this project is to create a piece of software that flexibly generates hardware to accelerate the evaluation of multiple layers of convolutions with a non-linear function called a ReLU (“rectified linear unit”) after each convolution.