Welcome to a minimalist guide to help beginners start on VHDL from scratch!
This guide does not cover how to upload a design to an FPGA, but it is a simple introduction to writing and simulating VHDL. It is recommended that you go from start to finish in order since some material builds on the previous.
Contents
- Setup: Download and setup an environment for modeling and simulating VHDL.
- Basic Gates: Learn about the basic skeleton of a VHDL code and different architectures.
- Flip-Flop
- Multiplexers
- Buses
- Registers: Expand the knowledge of Flip-Flops and learn how to create simple test benches.
- Adders: Use different concepts previously discussed and learn how to create more advanced test benches.
Feel free to fork, create pull requests, open issues, or just share with friends. I just hope this help others satisfy their curiosity on HDLs.